ARMdevices.net

Octavo Systems focuses on System-in-Package design: taking a microprocessor, DDR memory, power management and key passives, then collapsing them into a molded BGA that removes much of the hardest board-level integration. In this interview, that idea is shown not as an abstract packaging story but as a practical way to reduce layout risk, shrink PCB area, and accelerate bring-up for embedded Linux, edge AI, industrial control and audio products. https://octavosystems.com/

The most memorable demo is a Chaos Audio multi-effects guitar pedal, where the SiP handles the real-time audio DSP while a phone or tablet acts mainly as the control surface over Bluetooth. The point is not just miniaturization; it is deterministic local processing with effectively no audible latency, which is exactly what musicians need when switching tones, stacking effects, or building a digital pedalboard that still feels immediate under the fingers.

From there the discussion moves to Octavo’s newer processor-module direction, including the TI AM62-based OSD62PM and the STM32MP2-based OSD32MP2-PM reference platform. The pitch is very specific: processor plus DDR4 in a package roughly the size of the DRAM footprint, with major savings in area and routing complexity compared with a discrete MPU-and-memory design. Camera interfaces, DSI, LVDS, PCIe, Ethernet and built-in AI capability make these parts relevant for HMI, vision, smart gateways, robotics and compact edge compute gear.

What makes the booth tour useful is the range of deployed examples. Octavo shows SiP designs inside ROS 2 robotics modules, a retail people counter, a programmable smart torque drill for manufacturing, a compact SOM, an AMD Zynq UltraScale+ MPSoC platform for ADAS-style video inference, and an industrial automation controller with RS485, CAN and cloud connectivity. That broad spread makes the technology easier to understand: SiP is not a single market play, but a packaging and productization strategy that fits many embedded workloads.

A recurring theme is that SiP is not only about size. Octavo argues that pre-validating the processor-to-memory subsystem removes non-differentiating engineering work, reduces design spins, and in some cases can even compete on BOM cost when compared with sourcing the processor and DRAM separately. Filmed at Embedded World 2026 in Nuremberg, this is a grounded look at how integration, thermals, Linux-class processing and edge AI are being pushed into much smaller hardware footprints without turning every product into a custom high-risk board design.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=C9RZC3o2RHE

HS Devices presents Atronx as a compact embedded development platform built around a microQ7 computer-on-module and an Octavo System-in-Package approach, aimed at teams that need a ready hardware base for custom products rather than a finished end device. The pitch is clear: shorten hardware bring-up, keep software portable, and give engineers a practical Linux-based platform they can adapt for industrial control, monitoring, and edge-connected systems. https://www.hsdevices.com/

What stands out in the demo is the browser-based terminal and device management layer. Instead of treating the module as a black box, HS Devices shows telemetry, module details, CPU load, memory usage, temperature, and direct command-line access in one web interface. That makes the board feel less like a static eval kit and more like a remotely manageable embedded node, which is useful for prototyping field devices, service access, scripted deployment, and debugging across distributed installations.

The hardware story is about modularity and reuse. Atronx is positioned so developers can keep the same carrier or development board and swap compute modules depending on the target: more multithreaded Linux performance, lower power operation, or stronger real-time behavior. That kind of separation between carrier design and compute module is valuable in embedded product design because it reduces redesign cycles, preserves I/O investment, and lets teams move faster when requirements change late in development.

There is also an interesting small-company angle here. HS Devices is a startup from Niš, Serbia, focused on PCB design, circuit design, and embedded hardware engineering, and this product reflects that mindset: practical board-level integration, standardized software foundations, and attention to communication interfaces. Filmed at Embedded World 2026 in Nuremberg, the interview shows a company trying to turn board design expertise into a flexible embedded platform that engineers can actually build on, not just evaluate.

source https://www.youtube.com/watch?v=SIz9Ln5vz68

RISC-V CEO Andrea Gallo presents here not as a single chip vendor story, but as the governance layer behind an open instruction set architecture that lets semiconductor firms, IP providers, tool vendors and device makers build to the same ISA while keeping their own implementation details proprietary. The interview explains why that distinction matters: RISC-V is an open standard, not an open-source core, so the shared asset is the specification itself and the portability it enables across software stacks, supply chains and long product cycles. https://riscv.org/

A central theme is standardization. Andrea Gallo frames the 2025 milestone of RISC-V International becoming an ISO/IEC JTC 1 PAS submitter as more than a badge: it is a path toward formal international recognition for the ISA, which can matter in procurement, compliance, functional safety and regulated industrial design. That is especially relevant as RISC-V moves further from microcontrollers into application processors, automotive platforms, security architectures and compute infrastructure where interoperability and long-term governance carry real weight.

The conversation also gets into how technical consensus is built without turning the ISA into bloat. New extensions are expected to solve real multi-company problems, not one-off requests, and that discipline is what keeps the architecture coherent while still expanding into vectors, matrix processing and AI-friendly data handling. The software point is critical: vendors may differentiate in silicon, microarchitecture and performance, but developers still want one PyTorch, one TensorFlow backend, one toolchain target and a stable compliance model rather than fragmented ports.

Another useful insight is how RISC-V is organizing itself around both horizontal technologies and industry verticals. Alongside the core technical groups, the ecosystem is pulling in requirements from automotive, safety, data center, space, intelligent edge and robotics so that recommendations can map real workloads to the right ISA profiles, extensions and software expectations. That makes the story less about ideology and more about practical system design: where the standard should stop, where vendors should compete, and how to keep portability from compiler to firmware to OS and AI runtime.

What comes through most clearly is that RISC-V is no longer just a university-origin ISA associated with embedded experimentation. It is becoming a neutral coordination point for global compute development, backed by formal process, public technical review and a growing base of engineers, researchers and students who are treating the architecture as production infrastructure. Filmed at Embedded World 2026 in Nuremberg, this interview captures that transition well: from open ISA theory to the harder work of profiles, extensions, safety, matrix acceleration, ecosystem alignment and real deployment at scale.

source https://www.youtube.com/watch?v=4IoVgheSB2o

Espressif’s booth video is really about how far the ESP32 family has moved beyond basic IoT nodes into embedded vision, motion control, touch UI, wireless audio, and higher-bandwidth connectivity. The main demo centers on an ESP32-P4 robotic arm using on-device computer vision to detect colored blocks and trigger pick-and-place motion, which is a good fit for the P4’s dual-core RISC-V architecture, AI instruction extensions, MIPI camera/display support, hardware pixel processing, and H.264-capable multimedia pipeline. https://www.espressif.com/

What makes the robotic arm section interesting is that it combines local inference with networked control instead of treating edge AI and cloud AI as opposites. In the demo, OpenCV-style vision runs directly on the chip for offline detection, while wireless connectivity is used for function-call style interaction and remote control. That fits Espressif’s broader direction for the P4 platform: richer HMI, camera-based edge computing, and low-cost embedded systems that can still expose modern interfaces and automation logic. The handheld controller also points to ESP-NOW as a practical low-latency device-to-device control layer for responsive robotics and peripherals.

The middle part of the video broadens that story with touch and audio demos rather than staying narrowly focused on robotics. The piano example shows how Espressif is positioning capacitive touch as a stable UI input method for compact devices, while the small talking character demo shifts attention to voice interaction, directional audio capture, and sensor-driven movement. That combination matters because Espressif is increasingly covering the full edge stack: sensing, local processing, audio I/O, display control, and wireless backhaul, all in platforms that stay closer to MCU economics than full application-processor designs.

Another useful part of the booth tour is the segmentation across chips. The ESP32-H4 appears in the BLE audio and touch-control demos, which lines up with its role as a low-power dual-core RISC-V SoC for Bluetooth 5.4 LE, IEEE 802.15.4, LE Audio, PAwR, direction finding, and battery-powered devices with an integrated DC-DC converter. The sensor shuttle concept then shows Espressif’s modular approach to quick prototyping, where IMU, magnetic, environmental, display, lighting, microphone, speaker, and battery functions can be mixed around a compact controller rather than rebuilt for each proof of concept.

Filmed at Embedded World 2026 in Nuremberg, the last stretch of the video gives a glimpse of where Espressif is expanding next: not just low-power 2.4 GHz IoT, but also stronger wireless transport. The ESP32-C5, which reached mass production in 2025, brings dual-band Wi-Fi 6 plus Bluetooth LE and 802.15.4, while the newer ESP32-E22 adds tri-band Wi-Fi 6E as a connectivity co-processor across 2.4, 5, and 6 GHz. Put together, the booth is less about a single hero demo and more about Espressif building a ladder from simple sensors to edge AI vision, LE Audio, robotics, and higher-throughput connected devices.

source https://www.youtube.com/watch?v=21dSHwdn7pQ

Espressif uses this demo to show how far its MCU roadmap has moved beyond classic sensor nodes and simple connectivity. The centerpiece is the ESP32-P4, a dual-core RISC-V MCU aimed at richer HMI, multimedia and lightweight edge vision, paired here with a Riverdi 12.1-inch 1280×800 high-brightness industrial touch display. What stands out is not raw headline performance alone, but the fact that this class of GUI can run in an MCU environment with ESP-IDF and LVGL rather than requiring a heavier application processor. https://www.espressif.com/en/products/socs/esp32-p4

The discussion makes clear that Espressif is positioning the P4 as a serious display and interface device: MIPI support, camera input, vector instructions, pixel-processing acceleration, and a software stack that stays accessible to embedded developers. That creates an interesting middle ground between traditional microcontrollers and Linux-class SoCs. For product teams building control panels, industrial terminals, smart appliances, medical interfaces or compact vision-enabled devices, that balance of cost, power envelope and graphics capability is likely the real point of interest.

Another theme is software portability and ecosystem depth. The demo moves between ESP-IDF, LVGL, Embedded Wizard and Slint, while also touching on Rust support and open-source inference examples. Espressif’s approach remains closely tied to accessible tooling, broad community adoption and low barrier to entry, which is one reason the ESP32 family continues to show up in both commercial products and fast prototyping. The partner angle with Riverdi also matters, because industrial display vendors can turn a reference platform into something closer to a deployable subassembly.

Power management is the other major thread. The ESP32-C6 demo highlights Espressif’s split between high-power and low-power cores, showing how software design affects current draw far more than many teams initially expect. That is especially relevant for battery devices, wireless panels and always-on IoT endpoints. Filmed at Embedded World 2026 in Nuremberg, the booth tour also gives a useful snapshot of how Espressif now spans makers, industrial users and HMI developers rather than sitting in only one of those camps.

The wider portfolio shown at the booth reinforces that trajectory. Alongside P4-based HMI and camera demos, Espressif points to C-series RISC-V parts tailored for different wireless and memory requirements, plus the newly announced ESP32-E22 as a tri-band Wi-Fi 6E connectivity co-processor covering 2.4, 5 and 6 GHz. Put together, the story here is about modular architecture: compute where you need it, radio where you need it, and a path from compact MCU designs to more display-heavy and connected embedded products without abandoning the familiar ESP development model.

source https://www.youtube.com/watch?v=uVr0JxrOTfU

This interview frames N-iX as a broad engineering partner rather than a narrow outsourcing vendor. The key point is its one-stop model: embedded software, hardware design, mechanical engineering, connectivity, cloud, and data work can be combined into a single product-development flow, which matters when companies need faster prototyping, tighter hardware-software integration, and fewer handoffs across suppliers. https://www.n-ix.com/

The embedded team describes the practical side of that model well. Instead of focusing only on firmware, they talk about building real devices end to end, including enclosures, electronics, and product-level design decisions. That makes this less about coding capacity and more about full-cycle embedded engineering, where board design, RTOS or Linux software, wireless connectivity, mechanical constraints, validation, and manufacturability all need to line up.

A useful detail in the conversation is how N-iX uses platforms such as Raspberry Pi and Arduino. These are presented mainly as prototyping tools, but also as fast paths for proof-of-concept work where teams need to validate sensing, control logic, motion, and obstacle avoidance before moving to a more production-oriented architecture. The robotic arm demo fits that pattern: rapid iteration around edge control, object handling, and system behavior, with the prototype acting as a bridge between concept and deployable product.

The mention of Nordic Semiconductor also points to a more specific technical direction: low-power connected devices. That usually means Bluetooth Low Energy, battery-optimized wearables, asset trackers, sensor nodes, and other designs where power budgeting, radio performance, firmware efficiency, and long maintenance cycles matter as much as raw compute. Seen that way, the video is really about how an engineering services company positions itself across the full embedded stack, from early prototype hardware to connected edge and IoT product development. The interview was filmed at Embedded World 2026 in Nuremberg.

source https://www.youtube.com/watch?v=aZFiVUrnBLw

CTRL+N presents itself here as a Serbian engineering startup building both hardware and software around embedded systems, with a clear focus on IoT, RTLS, wearables and AI-enabled digital platforms for industrial use. In this interview, the company frames its value around practical field devices rather than generic demos, showing how sensing, positioning and human-machine interaction can be combined into compact products for real deployments. https://ctrln.tech/

The strongest use case in the video is railway safety. CTRL+N shows a digital signalling and worker-safety concept built on embedded electronics, wireless connectivity and precise location awareness, so field personnel can be tracked relative to infrastructure and hazards. That points to a broader architecture built around RTLS, low-power radios such as Bluetooth Low Energy, edge sensing and alert logic, where worker position, status and alarm conditions can be fed into a supervision layer rather than handled as isolated devices.

The wearable element is especially relevant because it turns the system into something operational at track level. A wrist-worn or body-worn node that can vibrate, flash alarms and report location or basic vital-state data is a practical embedded design problem: power budget, ruggedization, wireless reliability, latency and usability all matter more than consumer-style features. In that sense, the video is less about a gadget and more about occupational safety infrastructure built from embedded hardware, firmware and connected software.

Another interesting detail is the AI-assisted multimeter concept. Instead of treating a measurement tool as a passive instrument, CTRL+N describes a compact tester with a chatbot-style interface that helps technicians investigate rail-track faults and interpret readings locally. That suggests a direction where field diagnostics blend measurement electronics, embedded UI, contextual guidance and AI support, giving junior engineers faster troubleshooting workflows while reducing dependence on constant access to senior staff. The interview was filmed at Embedded World 2026 in Nuremberg, where that mix of rail tech, wearables, RTLS and AI-backed maintenance made CTRL+N stand out as a systems-oriented engineering company rather than a single-product vendor.

source https://www.youtube.com/watch?v=16uPvs8tFE8

Altium positions Octopart Discover as a step beyond classic component lookup, turning Octopart from a parts search engine into a system-level discovery workflow. The core idea in this interview is persistent design intent: engineers can start with requirements, narrow options by context such as power, performance, lifecycle status or sourcing constraints, and carry those decisions through architecture, PCB design and procurement instead of losing that reasoning between tools. https://octopart.com/octopart-discover

What stands out is the shift from part-centric filtering to electronics system design. Rather than only searching for a specific IC or passive, the platform is shown handling reference designs, functional blocks, simulation assets, CAD data, lifecycle flags, alternates and distributor availability in one flow. That makes the tool relevant not just for component engineers but also for embedded software teams, hardware architects, sourcing specialists and manufacturing teams trying to converge earlier on a viable BOM.

The demo also suggests a more interactive reference design workflow. Users can inspect schematics and PCB context, view board layers and 3D geometry, drill into component properties, compare alternates, and preserve technical questions asked to field application engineers around a given design choice. That is important because many embedded projects fail less on raw part search than on handoff friction: why a device was chosen, whether it remains recommended for new design, and what constraints shaped the original decision.

On the Octopart side, the scale still matters. The demo references a component database in the tens of millions, live pricing and stock visibility, distributor and manufacturer normalization, and BOM-level purchasing flows that can move from architecture to preferred sourcing channels with fewer spreadsheet exports. For engineers dealing with second-source strategy, compliance, availability windows, regional supply conditions or cost-down work, that combination of technical metadata and sourcing context is where the platform becomes more than search.

Filmed at Embedded World 2026 in Nuremberg, this conversation is really about how EDA, supply chain data and early system architecture are starting to merge. Octopart Discover is presented not as a closed CAD feature but as an open, cross-ecosystem layer that can connect reference designs, component intelligence, distributor data and downstream implementation tools. If Altium executes on that open workflow, it could make early-stage embedded design more traceable, more procurement-aware and much faster to move from concept to production.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=SL3y-r2sSuM

SiliconAuto is positioning itself as a new automotive semiconductor player focused on the control layer that sits between high-level compute and real-time vehicle behavior. In this interview, the company frames its first XMotiv M3 microcontroller as part of a broader move toward automotive HPC, MCU and high-speed interconnect architectures built for low latency, functional safety and deterministic motion control rather than consumer-style compute alone. https://www.siliconautotech.com/

The technical story is really about partitioning. Instead of forcing a central SoC to absorb every sensor, control and housekeeping task, SiliconAuto argues for distributing work across a safety-oriented MCU and companion devices that handle timing-critical jobs closer to the edge. That matters in ADAS and automated driving, where sensor fusion, bounded latency, power limits and fail-operational behavior all shape the system architecture more than raw TOPS alone.

The XMotiv M3 itself is described as a TSMC 28 nm automotive MCU built around an Arm Cortex-M33 at 160 MHz, with TrustZone, HSM, random-number generation, CAN FD, SPI, I2C, UART and a large GPIO budget. In the demo, it drives an adaptive driving beam reference design with matrix LED control, regional dimming, steering-linked light shaping and welcome-animation features. The interesting angle is not just the headlamp demo, but the attempt to move premium lighting control, reference code and faster integration paths into more mainstream vehicle programs too.

A second thread in the video is SiliconAuto’s work with ZF on an award-winning I/O architecture shown at Embedded World 2026 in Nuremberg. Here the MCU acts as a safety and system-management companion for a chip handling camera and sensor pre-processing, image signal processing, radar-related data paths and AI-assisted detection. The broader implication is a chiplet-friendly automotive compute stack where OEMs can mix performance SoC, AI accelerator and I/O domains with more flexibility, while reducing CPU overhead, DDR traffic and sensor-interface bottlenecks.

The digital-twin demos push that idea further by showing software, AI inference benchmarking and even robotic-arm control before final silicon is available. That early virtual-platform workflow is increasingly relevant for automotive, robotics and drone development, where validation time, toolchain maturity and faster concept-to-production cycles can be just as important as the silicon itself. Overall, the video shows SiliconAuto less as a single-chip launch and more as an attempt to define a modular automotive compute model around safety MCU, sensor pre-processing, ADB lighting, UCIe-era integration and real-time motion.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=sxBNICzdrFo

MediaTek’s Embedded World 2026 booth tour centers on a broader edge AI compute stack for industrial and embedded systems, with the Genio family now spanning entry, mid-range, and higher-performance tiers. The key message is platform continuity: shared software direction, scalable AI acceleration, and pin-compatible options that let OEMs move between performance classes without redesigning everything from scratch. In practice, that matters for robotics, HMI, smart retail, machine vision, industrial IoT, and connected equipment that need on-device inference rather than cloud dependence. https://www.mediatek.com/products/iot/genio-iot

The newly discussed Genio 360 is positioned as a major refresh of the lower end of the lineup, replacing a much older class of part with a hexa-core 6nm design and up to 6 TOPS for edge inference. That is a meaningful jump for cost-sensitive devices that still need practical AI workloads such as object detection, pose estimation, gesture recognition, vision-based monitoring, and lightweight generative AI at the edge. Above that, the Genio 420 extends the range, while the previously introduced Genio 720 and 520 bring 10 TOPS on 6nm silicon with octa-core CPU configurations and support for LPDDR4 or LPDDR5 memory.

At the top of this discussion is the new Genio Pro tier, presented here as a 50 TOPS class platform aimed at heavier edge AI and robotics workloads. That shifts MediaTek’s embedded portfolio closer to use cases involving multimodal perception, larger vision models, more demanding transformer inference, autonomous mobile systems, and local LLM deployment in the 7B class and beyond, depending on model optimization, quantization, memory footprint, and thermal design. The emphasis is not only raw TOPS, but a combination of CPU headroom, multimedia capability, memory bandwidth, and developer readiness through early kits and partner designs.

The demo ecosystem in the booth shows how that silicon strategy turns into deployable products. MediaTek highlights partner SOMs and OSM modules, including compact designs from companies such as Mitwell, plus embedded boards built around parts like the Genio 1200 for display-heavy systems. One of the more concrete examples here is a 6DoF tracking setup for forklifts and mobile equipment, illustrating how edge AI, sensors, and embedded compute can be packaged into aftermarket or OEM industrial systems. Filmed at Embedded World 2026 in Nuremberg, the video gives a useful snapshot of where MediaTek is heading: from entry-level embedded AI up to high-throughput edge compute for robotics, vision, and industrial automation.

source https://www.youtube.com/watch?v=gtCAVdaedqI

Premio’s latest platform story is really about rugged edge compute becoming more modular, more serviceable, and more AI-specific at the same time. The interview focuses on fanless industrial computers, panel PCs, and display systems designed for harsh deployments where vibration tolerance, thermal design, and lifecycle flexibility matter as much as raw performance. A central theme is Premio’s EDGEBoost architecture, which lets users configure I/O, storage, networking, and acceleration around a standardized core rather than forcing a fixed box into every deployment. https://premioinc.com/

That modular approach shows up in several places: M12 connectivity, dual 10GbE, PoE, out-of-band remote management, lockable storage, safe-eject logging features, and expansion paths for NVMe and GPU resources. The pitch is not just customization for its own sake, but faster deployment in industrial environments where requirements vary between vehicle systems, rail, machine vision, data logging, and field-installed automation. Premio also ties this to IEC 62443-4-1 processes, which matters for customers now treating cybersecurity and maintainability as part of the hardware spec rather than an afterthought.

The strongest technical segment is around rugged AI computers based on NVIDIA Jetson, especially Jetson AGX Orin and Orin-class systems for robotics, surveillance, ADAS, and anomaly detection. The transcript highlights GMSL camera support for low-latency long-cable video links in trucks and rail, plus IP66 designs for condensation-prone deployments. That combination of sealed enclosure design, fanless thermal engineering, and transport-focused compliance such as EN50155 and E-Mark is what makes these systems relevant beyond the demo table and into real railway and in-vehicle edge AI rollouts.

Another useful angle is Premio’s view of the “physical AI” compute ladder. At the low end, x86 platforms with integrated NPUs handle compact fanless inference. Moving up, M.2 AI accelerator cards add higher channel density for vision workloads without the power and size penalty of multiple discrete GPUs. Then Jetson Orin and larger GPU-based x86 systems take over for vision-language models, multimodal inference, and on-prem industrial AI where bandwidth, privacy, and latency make cloud-first architectures less practical. Filmed at Embedded World 2026 in Nuremberg, the interview reflects a market that is clearly shifting from simple object detection toward local VLM, SLM, and multimodal edge deployments.

The smart terminal and OEM/ODM sections complete the picture. Premio is not only selling rugged boxes, but also modular display systems where damaged front-end panels can be replaced without scrapping the compute backend, which is a practical design choice for glove-heavy industrial use. Combined with board-level customization, waterproof housings, and tailored I/O, the company is positioning itself as a hardware partner for system integrators building industrial 5.0, smart city, inspection, surveillance, and robotics platforms where reliability, thermal validation, and configurability all have to coexist.

source https://www.youtube.com/watch?v=rEmbvGBsz4I

Innatera is positioning neuromorphic computing as a practical way to run always-on sensor AI without the usual power penalty. In this interview, the company explains how its Pulsar chip combines spiking neural networks, a RISC-V microcontroller, and a CNN accelerator in a single sensor-edge device, so pattern recognition can happen continuously where data is created rather than being pushed to a larger processor or the cloud. That makes the discussion less about raw TOPS marketing and more about system-level efficiency, latency, and battery life. https://innatera.com/pulsar

The key idea is that Pulsar uses silicon neurons and synapses across digital and analog spiking fabric to process sensory events in a brain-inspired way. Instead of treating AI as a separate block bolted onto a conventional embedded design, Innatera presents neuromorphic inference as part of the whole SoC architecture. The result is a platform aimed at sub-millisecond reaction time, low data movement, and ultra-low-power operation for audio, radar, vibration, and other continuous sensor streams at the edge.

What makes the video interesting is that the story quickly moves from architecture to concrete product categories. The live demos include real-time audio classification, audio scene recognition for adaptive headphones, radar-based human presence detection, and predictive maintenance based on vibration sensing. These are all workloads where conventional embedded AI often struggles with the tradeoff between accuracy and always-on operation. Innatera’s claim is that spiking neural networks can keep sensing active full time while staying inside the power budget of compact battery-powered devices.

There is also a strong ambient intelligence theme running through the interview. A notable example is the radar-based human presence detector developed with Socionext, targeting extremely low-power detection for devices such as smart doorbells. Another is the intelligent smoke detector described here, which adds classification and occupancy awareness rather than acting as a simple threshold alarm. Filmed at Embedded World 2026 in Nuremberg, the demo set gives a useful snapshot of where neuromorphic edge AI is heading: not as a research novelty, but as embedded silicon for smart home, industrial IoT, wearables, and safety systems alike.

The company background matters too. Innatera spun out of Delft University of Technology in 2018 after years of research into brain-inspired and energy-efficient computing, and the interview frames Pulsar as the point where that research becomes production silicon. That matters because the value proposition is not generic AI acceleration, but embedded pattern recognition that can stay on continuously in the field. For engineers building sensor-rich products, this is really a discussion about edge inference architecture, mixed-signal design, SNN deployment, and how to reduce power, latency, and bandwidth all at the same time.

source https://www.youtube.com/watch?v=jAM-sgLlmrg

Bosch Rexroth is positioning ctrlX OS as a hardware-independent industrial Linux platform for software-defined automation, where the same application stack can move across controllers, IPCs, edge systems and virtual environments. In this interview, the focus is on secure industrial control, app-based deployment, and a common runtime that lets developers build once and roll out across multiple device classes with far less integration work. https://www.ctrlx-os.com/

The demo shows how ctrlX OS can host different control approaches on the same data layer, from a soft PLC to Node-RED, while exposing machine states and digital I/O through a unified interface. That matters because industrial edge systems increasingly mix classic control logic, visualization, protocol handling, and data services on one platform rather than splitting them across isolated boxes.

A key theme here is the broader hardware reach created by Bosch Rexroth’s work with AMD. The transcript points to support for CPU, GPU and MPU resources, which fits the current push toward x86 embedded processors and adaptive SoC platforms for edge compute. For developers building process-hungry workloads, that opens the door to more demanding HMI, analytics and edge AI pipelines without changing the operating-system layer or rewriting the deployment model.

Security and lifecycle management are just as central as performance. ctrlX OS is presented here as CRA-ready and aligned with IEC 62443-4-2 Security Level 2 expectations, while also giving access to the practical features engineers actually need in the field: backup and restore, reset, license management, app installation, and centralized access to every exposed data point. The result is less about a single controller and more about a secure, manageable OT software platform.

What makes the story interesting is the developer angle. Bosch Rexroth is clearly pushing an API-driven model where the same functions available in the web UI can also be automated through REST APIs, virtual controllers, SDK tooling, and reusable apps. Filmed at Embedded World 2026 in Nuremberg, this interview captures a broader transition in industrial automation: PLC logic, low-code tools, edge AI acceleration, and secure app deployment are starting to converge into one programmable software stack.

source https://www.youtube.com/watch?v=zIA8jK-tkFE

Tianma’s display portfolio here is less about a single panel and more about how the company is packaging complete HMI platforms for industrial, medical, transport and automotive use. The interview moves from a 23.8-inch 4K2K industrial display to integrated systems where Tianma supplies not just the LCD or OLED, but also electronics, compute boards and enclosure design. That matters for OEMs building camera monitors, control terminals or specialized vision devices, because the value shifts from raw panel supply to full module integration, long-life support and design-in flexibility. https://www.tianma.eu/

A big theme in the booth tour is optical engineering for difficult environments. Tianma shows glass-free 3D with eye tracking, allowing a split between 2D UI and 3D visualization, which fits medical imaging and other workflows where depth cues matter but operators still need conventional data overlays. Mini-LED backlighting with local dimming is another clear focus, improving black levels and contrast for medical and inflight display use, while reflective display technology targets outdoor readability with far lower power draw than a conventional transmissive panel.

The industrial side is paired with application-specific hardware concepts, including a rugged professional tablet style monitor for camera and vision systems. What stands out is the combination of Tianma’s core display technologies with embedded electronics, suggesting a path from display component to near-finished device. The transcript also points to Rockchip-based electronics in the demo hardware, which reinforces the idea that Tianma is not just talking about panel specs, but about complete embedded display subsystems tuned for field use, sunlight readability and power efficiency.

On the automotive side, the most interesting pieces are transparent Micro-LED, long-shape Micro-LED formats and a Micro-LED source for head-up display architecture. That lines up with Tianma’s broader recent push into automotive Micro-LED and HUD concepts, including very high brightness projection-oriented displays and transparent surfaces that can turn glass areas into information layers. In that context, the booth demo feels like an extension of a wider strategy around smart cockpit display architecture, where LTPS LCD, AMOLED and Micro-LED each serve different HMI roles rather than competing as one universal technology.

Later in the video, filmed at Embedded World 2026 in Nuremberg, the broader message becomes clear: Tianma is positioning itself as a global display engineering partner with in-house coverage across TFT-LCD, LTPS, AMOLED, Mini-LED and Micro-LED, backed by manufacturing scale in Asia and regional support for European customers. The result is a story about display roadmaps, integration capability and application fit, from smartphones to digital signage to transportation and automotive cockpits, rather than a simple product launch.

source https://www.youtube.com/watch?v=r51NNAA56PY

Axelera positions itself as a European edge AI alternative focused on inference rather than training, and this interview makes that distinction clear. The main story is performance per watt: the company’s Metis platform is presented as delivering 214 TOPS at around 6W typical power, in compact M.2 and PCIe form factors that let developers add AI acceleration to existing x86 or Arm systems without redesigning the whole box. https://axelera.ai/

What stands out in the demo lineup is how practical the workloads are. Instead of benchmark theatre, the booth focuses on edge deployments such as native 8K video analytics, retail loss prevention, container inspection for rust and damage, and autonomous robotics. The point is not just raw throughput, but being able to process high resolution video streams and multiple models at the edge where thermal limits, latency, bandwidth, and total system cost matter more than in cloud-first AI.

The technical angle is also stronger than a typical trade-show pitch. Axelera describes Metis as combining digital in-memory computing for matrix-vector multiplication with a RISC-V based orchestration layer across four AI cores, which allows parallel or cascaded model execution. That architecture fits the current edge AI mix well: computer vision pipelines, multimodel workloads, and lighter generative AI tasks such as speech interfaces and small language models, rather than full-scale training or oversized server-class LLM deployments.

The roadmap matters just as much as the current chip. In the interview, Axelera points to Europa as the next step for premium edge systems, robotics, VLM-style contextual understanding, and larger language models beyond the current memory envelope. That lines up with the company’s broader push this year around Metis and Europa, its Voyager SDK toolchain, and ecosystem work that makes model conversion and deployment easier for developers moving from FP32 training environments to efficient edge inference.

Filmed at Embedded World 2026 in Nuremberg, this conversation shows why Axelera is getting attention in European semiconductor and edge AI circles: not because it claims to replace GPU training infrastructure, but because it targets the part of the stack where many industrial systems actually live. Low-power inference, compact accelerators, RISC-V control, DDR5-backed memory bandwidth, and deployable computer vision pipelines are the core themes here, with Europe’s supply-chain and sovereignty angle sitting in the background rather than dominating the pitch.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=iJrwV9zM53A

ProvenRun is making a case for embedded security that starts below the application layer, with a mathematically verified trusted base rather than another add-on middleware stack. In this interview, the company explains how ProvenCore, its formally proven secure OS and TEE, is used to build high-assurance systems for automotive, avionics, defense, microcontrollers and cloud security, with the goal of reducing attack surface, simplifying certification and keeping long lifecycle products maintainable. https://provenrun.com/

A big part of the discussion is the shift to software-defined vehicles and zonal automotive Ethernet. ProvenRun’s protocol-break approach fully deconstructs and reconstructs traffic between exposed domains and safety-critical zones, rather than relying only on segmentation. That matters for in-vehicle infotainment, connectivity modems and ADAS paths, where 1GbE and faster links now carry far more critical traffic than older in-car networks ever did.

The technical differentiator is formal methods. ProvenRun says ProvenCore remains the only operating system certified at Common Criteria EAL7, and that foundation is then reused for trusted applications such as secure storage, cryptography, PKCS#11, VPN, network stacks, secure firmware update and protocol filtering. The company also highlights compatibility with standard embedded security ecosystems including GlobalPlatform, PSA-style APIs, Android trusted applications and post-quantum cryptography work with CryptoNext.

The interview also touches the microcontroller side, where ProvenCore-M is positioned as a secure RTOS and TEE for Arm v8-M class devices, including ST deployments around STM32 security architectures. That gives developers a pre-certified route to TrustZone-based isolation, secure services and easier product evaluation without having to design every security primitive from scratch. Filmed at Embedded World 2026 in Nuremberg, the demo shows how that same security-by-design philosophy is now being stretched from MCU roots into automotive gateways and trusted edge compute.

On the cloud side, ProvenRun is pushing ProvenHSM and ProvenBox as remotely manageable hardware-backed trust anchors for key management, crypto services and customizable secure applications. The interesting angle is not just HSM throughput, but compositional certification, cloud-native administration, FPGA-assisted crypto acceleration and a roadmap that includes PQC readiness. Overall, this is a useful look at how embedded cybersecurity is moving toward verifiable isolation, certifiable trusted execution and longer-term lifecycle assurance across both edge and data center scale.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=Cmz3ENmAYPs

eSOL positions itself as a full-stack embedded software partner rather than a vendor selling only one RTOS layer. The core message in this interview is integration: a production-ready platform that combines the eMCOS real-time operating system, a POSIX-compliant profile, middleware for networking and robotics-oriented workflows, plus engineering services that extend from bring-up to certification. That matters for teams trying to reduce supplier fragmentation and keep one accountable path from hardware integration to deployed code. https://www.esol.com/

A key theme is the gap between prototype software and certifiable production systems. The demo points to ROS and model-based toolchains as part of the ecosystem, but the argument from eSOL is that open robotics frameworks alone are not always enough once determinism, safety, and real-time behavior become mandatory. In that context, eMCOS POSIX is presented as a way to preserve familiar POSIX development models while moving toward tighter scheduling control, certification targets, and system-level integration for embedded products.

What makes the platform interesting technically is scalability across compute classes. In the demo, the same runtime approach spans ARM Cortex-M, ARM Cortex-R, ARM Cortex-A and also RISC-V, reflecting eSOL’s long-standing focus on multi-core and many-core embedded architectures. That gives the interview a broader angle than a simple RTOS pitch: it is really about one software foundation that can move from small microcontrollers to larger heterogeneous SoCs without forcing a complete tooling reset or a redesign of the application stack at every step.

Recent eSOL direction adds useful context to what is shown here. The company has been expanding its Full Stack Engineering model in Europe, and its eMCOS POSIX profile gained ISO 26262 ASIL D compliance in 2025, which reinforces the interview’s emphasis on automotive-grade real-time software. eSOL has also been showing eMCOS in software-defined vehicle workflows, including virtual-platform work around Renesas R-Car, so the message here fits a wider industry push toward software-first development, safety partitioning, and faster validation at scale.

Overall, this is less about Linux replacement rhetoric and more about where a deterministic POSIX RTOS fits when embedded teams need predictable latency, certification support, multicore scaling, and one engineering interface across the stack. The interview was filmed at Embedded World 2026 in Nuremberg, and it frames eSOL as a company targeting automotive, robotics, industrial and medical designs where middleware compatibility, long-term support, and integration ownership are often worth as much as raw kernel features in practice here.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=iEaaI6PVweQ

ATGBICS is positioning itself as a practical supplier for industrial network connectivity rather than just another optics reseller. The main story here is compatibility at scale: transceivers for more than 300 vendor ecosystems, support for legacy and current modules, and a business model built around keeping networks running when original OEM parts have gone end-of-life. That matters in embedded and industrial systems where redesigning around a discontinued optical part can be far more expensive than the module itself. https://atgbics.com/

A big part of the discussion is obsolescence management. ATGBICS describes a process where the bill of materials is locked, prototype samples can be validated against a customer’s hardware, and repeat orders can be built with the same chipset, laser, and configuration that was previously qualified. For industrial Ethernet, long-lived automation platforms, transport systems, and ruggedized infrastructure, that kind of traceability can be more important than chasing the newest data rate.

The interview also makes clear that this is not only about old through-hole optics from the 1990s. The portfolio shown moves from 1×9 and 2×5 legacy transceivers to 1G and 10G workhorse SFP-class modules, then all the way up to high-bandwidth QSFP and direct attach cable options used in data center and AI networking. The interesting angle is that the same company is covering both ends of the market: replacement parts for installed industrial gear and compatible modules for newer high-density switching environments.

What gives the video some depth is the manufacturing and customization side. ATGBICS talks about working with factory partners in Taiwan and China, offering certificates of conformity, custom firmware, private labeling, and barcode-level branding for OEMs building their own switch, router, or PoE product lines. Filmed at Embedded World 2026 in Nuremberg, the interview shows how optical connectivity is increasingly tied to supply-chain resilience, second-source qualification, and lifecycle planning, not just raw bandwidth.

The result is a useful look at a part of embedded infrastructure that usually stays in the background. Instead of focusing on headline silicon, this conversation is about pluggable optics, DACs, AOCs, OEM-compatible coding, industrial temperature requirements, and the economics of keeping deployed systems alive for years longer than the original vendor may support. That makes the video relevant for engineers, sourcing teams, EMS partners, and network equipment makers dealing with both legacy maintenance and forward migration.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=h5iWToDbxh4

Weebit Nano is positioning ReRAM as an embedded non-volatile memory alternative to flash for SoCs that need faster writes, lower power, better endurance, and easier scaling below 28 nm. In this interview, CEO Coby Hanoch explains why the company focuses on embedded NVM rather than bulk storage: the target is firmware, security keys, calibration data, AI coefficients, and instant-on system behavior integrated directly on the same die as compute and control logic. https://www.weebit-nano.com/

The key technical point is that Weebit’s ReRAM is a back-end-of-line technology, built between metal layers rather than in the silicon substrate. That matters for mixed-signal and analog-heavy designs, because it avoids many of the layout and process compromises associated with embedded flash. Hanoch describes the cell in simple terms: voltage moves ions to form or break a conductive path, switching between low and high resistance states that represent stored data.

For edge AI, the pitch is especially clear. If model coefficients can live in embedded non-volatile memory on the AI chip, designers can avoid a separate external flash device, reduce board cost, shorten boot time, cut power draw, and remove a security exposure created when weights are copied at startup. That fits near-memory compute, and it also points toward in-memory compute, where analog-style ReRAM arrays may eventually support more efficient AI inference for gesture recognition, sensor workloads, and always-on edge devices.

The interview also shows why this matters beyond AI. Embedded ReRAM is relevant for power management ICs, MCUs, IoT nodes, automotive electronics, and aerospace-oriented designs that need retention without power, robust endurance, and tolerance for harsh conditions. Weebit highlights qualification work for automotive temperature ranges, radiation immunity as a useful characteristic, and the benefit of integrating memory without disturbing the optimal analog portion of a chip.

Filmed at Embedded World 2026 in Nuremberg, the discussion captures a memory company moving from R&D into commercialization. Weebit already talks about customers such as onsemi and Texas Instruments, growing capacity targets in the embedded range, and a roadmap that connects embedded NVM with future AI architectures. The result is not “more storage” in the consumer sense, but a more integrated memory block for edge silicon where power, cost, area, boot latency, and security all matter at once.

All my Embedded World videos are in this playlist: https://www.youtube.com/playlist?list=PL7xXqJFxvYvjgUpdNMBkGzEWU6YVxR8Ga

source https://www.youtube.com/watch?v=dn82VxEX4aI

Tektronix focuses here on one of the harder measurement problems in modern power electronics: capturing fast, high-voltage switching behavior without corrupting the waveform through probe loading, ground noise, or isolation limits. The interview centers on the second-generation IsoVu isolated voltage probe, where optical power delivery over glass fiber lets the probe head stay electrically isolated while still measuring very small and very fast events. That matters for SiC and GaN power stages, where dv/dt, common-mode noise, and switching transients quickly expose the limits of conventional probing. https://www.tektronix.com/

A key point in the demo is flexibility at the probe tip. The discussion mentions interchangeable tips spanning low-voltage work up to kilovolt-class measurements, which fits the broader need to move between gate-drive, shunt, switch-node, and bus measurements without rebuilding the whole setup. Tektronix also highlights its isolated current probing, including an RF link architecture with no direct physical connection inside the probe path, aimed at very high common-mode rejection. In practice, this is the kind of tooling engineers need for double-pulse test setups, power integrity analysis, wide-bandgap converter design, and validation of fast-switching inverter stages. ([tektronix.com][1])

What makes the video interesting is that it is less about headline specs and more about measurement credibility. The screen demo compares a reference voltage with current captured through the isolated current probe, showing how Tektronix is positioning these probes as part of a complete power integrity workflow rather than as standalone accessories. That fits a broader shift in lab instrumentation, where probe architecture, tip ecosystem, connection standards, and noise rejection are becoming just as important as oscilloscope bandwidth. The clip was filmed at Embedded World 2026 in Nuremberg, where this kind of test and measurement detail is especially relevant for embedded power, automotive, industrial control, and energy conversion teams.

The booth tour also briefly points to Tektronix’s wider high-speed instrumentation stack, including the 7 Series DPO at up to 25 GHz and 125 GS/s, plus the DPO70000SX platform, which Tektronix lists up to 70 GHz and 200 GS/s for very high-speed serial, PCIe, memory, and signal-integrity work. So the story here is really two layers of debug: precision isolated probing for power devices such as SiC and GaN MOSFETs, and high-bandwidth scope platforms for the digital and interconnect side of the same system.

source https://www.youtube.com/watch?v=kev976LKlLg