Cerebras founder and chief architect Michael James walks through the CS-3 system and its wafer-scale engine, a single 300 mm die integrating around a million AI-optimized compute cores on one piece of silicon. Built in 5 nm with roughly 4 trillion transistors, WSE-3 delivers on-chip memory, interconnect and compute in one monolithic device, targeting high-throughput AI inference and data-intensive HPC workloads in a compact rack-scale node. https://www.cerebras.ai/chip
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He explains the extreme power-delivery and packaging needed to run this chip at roughly 25 kW: front-side AC/DC modules, 3D power distribution and dense arrays of regulators positioned close to the wafer to manage around 30,000 amps of current. Because all compute and 44 GB of SRAM sit on a single wafer, the system minimizes off-chip traffic and uses control logic that smooths power ramps with dummy operations when workloads switch off, avoiding destructive current spikes while preserving energy efficiency.
On the architecture side, James describes the WSE-3 as a proprietary dataflow processor designed for strong scaling. Loop induction variables, data movement and network behavior are encoded directly into the instruction set, so a single matrix operation can be spread spatially across the full grid of cores with minimal software overhead. That allows Cerebras to map full transformer layers over the wafer and reach very high inference throughput, with customers reporting large speedups over Nvidia GPU clusters on latency-sensitive language-model serving.
The discussion then shifts to real workloads, including a global shallow-water-equation simulation of an asteroid impact off California, run at about 200 m resolution over the entire planet. By exploiting the dense on-wafer memory and mesh interconnect, a cluster of CS-3 nodes achieved exascale-class performance for this tsunami scenario at a fraction of the power draw of traditional exascale systems, while still supporting large language models such as Llama and DeepSeek on the same architecture.
Filmed at Supercomputing 2025 in St Louis, the interview also touches on manufacturing yield and roadmap. Cerebras overprovisions identical cores across the wafer and then uses automated defect mapping plus constraint solving to reroute communication around faulty regions, guaranteeing at least 900,000 working cores per device and turning the rest into pass-through fabric. James hints that future generations will continue this wafer-scale path, pushing AI inference and physics-based HPC further by co-designing architecture, packaging and dataflow software as a single system.
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