Cavium demonstrates a high performance implementation of ODP-IPSec packet processing on a Cavium MIPS SoC on both Linux-Userspace and Bare Metal runtime environments. The demo is able to produce 40GB/s IPSec ESP processing.
Demonstrate the performance effective implementation of ODP-IPSec packet processing on Cavium SoC on Linux-Userspace and Bare Metal runtime environments.
IPSec ESP Processing (Authentication and Cipher)
40G Line rate
Linux User Mode environment support
Bare metal environment support
AES-CBC Cypher ( RFC 3602)
HMAC-SHA1-96 Authentication (RFC 2404)
Multiple SA support
Direct access to perf counters for Networking/ODP domain really helps to budgeting lower CPU cycles to Benchmark Data Plane. Demo shows POC about Accessing Perf counters with Perf syscall Vs Direct access of perf counters from Userspace. Implementation has been shown for ArmV7 ( Arndale ) Board and ArmV8 ( Juno ) Board. Yogesh Tillu, Linaro/Cavium Engineer has demoed 1st cut implementation of concept.
Cavium launches the world’s fastest ARM Processor in their family of workload optimized ThunderX 64bit ARMv8 Server Processors (including ThunderX_CP for Cloud, ThunderX_ST for Storage, ThunderX_SC for Security and ThunderX_NT for Networking), for a range of applications in the cloud and data center. With 48 cores running at 2.5GHz each, ThunderX is the world’s highest performing low-power 64-bit ARMv8 SoC family of workload optimized processors with a range of SKUs and form factors for high performance volume compute, storage, secure compute and networking specific workloads. Analysts predict that the global data center infrastructure market, including servers, storage, networking, security and virtualization, will reach $128 billion in 2014. Cavium is hereby taking their share of that market by releasing their extremely high performance custom design ARM Server processor.
This product family is based on highly efficient full custom processor cores designed by Cavium in 28nm process technology under architectural license from ARM. It is fully compliant with ARMv8 architecture as well as ARM’s Server Base System Architecture (SBSA) standard while bringing to market dramatic enhancements that include:
-The first ARM based SoC that scales up to 48 cores with up to 2.5 GHz core frequency with 78K of I-Cache and 32K of D-Cache along with 16MB of L2 cache.
– The first ARM based SOC to be fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI™)
– Integrated I/O capacity with 100s of Gigabits of I/O bandwidth
– Four DDR3/4 72 bit memory controllers capable of supporting 2400 MHz memories with 1TB of memory in a dual socket configuration
– Hundreds of integrated hardware accelerators for security, storage, networking and virtualization applications.
– Standard based low latency Ethernet fabric interconnecting thousands of ThunderX™ nodes in 2D and 3D configurations and enabling fabric monitoring and SLA enforcements with awareness and policy enforcement for virtualized networks.
– Virtualization everywhere with Cavium virtSOC™ technology – Full system virtualization for low latency from virtual machine to I/O.
– Best in class performance per watt and performance per dollar for the target applications
Cavium talks about and shows their latest enterprise, data center, wired and wireless networking OCTEON and OCTEON Fusion SoCs based on ARMv8 64bit and MIPS, making customized optimized core designs for each in use for cloud servers and base stations among other. CAVIUM claims that their ARMv8 64bit enterprise/server design, due to be released later this year, provides more performance at lower power consumption than Intel´s x86.