Dell PowerEdge XE9785L: 8x AMD Instinct MI355X, EPYC, 3U direct liquid cooling

Posted by – December 26, 2025
Category: Exclusive videos

From the Dell booth at Supercomputing SC25 in St. Louis, this walkthrough focuses on a compact AI platform labeled “XC9785” on-site (likely the PowerEdge XE9785L naming), pairing dual-socket AMD EPYC CPUs with eight AMD Instinct MI355X accelerators for both training and inference. MI355X targets dense, memory-forward AI/HPC, with up to 288GB HBM3E per GPU, roughly 8TB/s memory bandwidth, and expanded low-precision formats (MXFP6/MXFP4) aimed at better throughput-per-watt when models are memory-bound rather than ALU-bound. https://www.dell.com/en-us/shop/ipovw/poweredge-xe9785l


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A useful detail is the bare GPU board shown without cold plates or heat sinks, which makes the packaging constraints obvious: power delivery, signal integrity, and coolant routing all sit centimeters apart. Dell frames the XE9785L as a 3U direct-liquid-cooled design intended for OV3 (OCP Open Rack v3) deployments in IR7000/IR9000 racks, where shared manifolds and blind-mate interfaces enable higher rack density while keeping service steps predictable in a packed rack.

Next to the accelerator chassis, they point to storage-heavy compute nodes built around AMD’s latest CPUs: up to 24 direct-attached U.2 NVMe drives, with an on-the-spot claim of roughly 300Gbps of storage throughput, plus PCIe Gen5 full-height expansion for high-speed networking. In practice, that maps to the less glamorous but critical parts of AI: fast local NVMe for checkpoints, data staging, and feature/vector stores, then high-bandwidth I/O for scale-out fabrics and NVMe-oF style data paths.

The clearest spec callout is power: MI355X can run up to about 1.4kW per GPU in a liquid-cooled configuration, which is why rack-level cooling architecture, monitoring, and leak-risk mitigation start to matter as much as raw accelerator count. The takeaway is a rack-ready building block for converged HPC and AI workflows—dense GPU compute, PCIe Gen5 I/O, and NVMe-rich nodes designed to keep data moving as aggressively as matrix math in deployment.

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