RIKEN’s FugakuNEXT program is framed as a 2030 deployment that builds on what Fugaku (deployed in 2020) did well for large-scale science: strong FP64 throughput for conventional simulation, and a software ecosystem tuned for production HPC. The pitch here is that the next decade’s workload mix is shifting toward hybrid AI + simulation, so the system architecture needs to treat AI performance as a first-class goal rather than an add-on. https://www.fugaku.riken.jp/
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On the CPU side, the discussion centers on Fujitsu’s ARM-based roadmap (the transcript references the current-generation CPU and its move to leading-edge process nodes) and the idea of a richer SoC that could also integrate an NPU alongside general-purpose cores. The key technical tension is familiar in exascale planning: keep strong FP64 for numerics, while also improving throughput per watt for AI-relevant kernels, memory bandwidth pressure, and node-level balance, without locking the platform into a single workload style.
For accelerators, they explicitly assume GPUs will be in the loop, citing NVIDIA’s recent high-end generations (Blackwell) and the following roadmap (Rubin), with the expectation that FugakuNEXT will land after that point. In practical terms, that implies heavy reliance on mixed precision (FP16/BF16/FP8), tensor-style matrix engines, and high-bandwidth memory, while still keeping a path for double-precision science and deterministic numerics when the application demands it at scale.
A lot hinges on the CPU–GPU connection: PCI Express is named as an option, alongside an “NVLink-class” approach, but the bigger requirement is cache-coherent behavior between CPU memory and GPU memory so programmers can treat the machine less like loosely coupled devices and more like a coherent heterogeneous node. They also point to the program mechanics behind that goal—testbeds, coding and code-design strategy, evaluation loops, and a timeline that aligns facility build-out with system integration and software readiness to make it.
What comes through is an HPC roadmap that assumes AI isn’t separate from simulation anymore: think surrogate models inside solvers, learned preconditioners, data assimilation, and large-scale training/inference running next to classic MPI-heavy workloads. The project is presented as a coordinated effort with leadership and support teams, plus an expanded datacenter footprint to host the next platform, reflecting how much of “supercomputer design” is now co-design across silicon, interconnect, cooling, compilers, and production operations for reliability at scale today.
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