Forlinx presents itself here as more than a module vendor. The interview is really about how an embedded hardware company is moving up the stack into edge AI integration, combining SoM design, carrier boards, manufacturing, software enablement, model conversion, and deployment support. The main message is that Forlinx wants to shorten the path from silicon vendor roadmap to a production-ready embedded AI platform, whether the target is industrial vision, smart gateways, robotics, or local multimodal inference. https://www.forlinx.net/
The headline demo pairs an NXP i.MX 95 platform with the Ara240 M.2 AI accelerator, creating a hybrid edge AI system that mixes the i.MX 95’s local vision, graphics, security and low-power processing with an external 40 eTOPS accelerator for larger models. In the discussion, that translates into local image understanding and natural-language analysis without relying on cloud inference, including a 7B-class LLM workflow and token generation around 20 tokens per second. That combination is interesting because it shows a practical split between on-chip NPU inference and a higher-throughput PCIe add-in path for generative AI at the edge.
A second thread in the video is platform scaling. Forlinx talks about using the i.MX 95’s own NPU for front-end recognition and then handing richer tasks to the accelerator, while also pointing to multi-card configurations for larger parameter counts. That makes the story less about one benchmark and more about architecture: modular edge AI, where compute can be right-sized from compact fanless designs up to multi-accelerator systems, depending on camera count, model size, latency target, and power budget.
The Rockchip side of the booth broadens that picture. RK3588 appears as a mature edge vision platform handling multi-camera workloads, PoE-connected inference pipelines, stitching, and video-centric AI optimization across encode, decode, and NPU execution. There is also a smaller RV1126B face-tracking demo showing how low-power Cortex-A53 class systems with an integrated NPU can still deliver responsive, fanless vision tasks. What stands out is not just chip support, but the engineering work behind BSP tuning, driver maturity, model adaptation, and layer-level optimization for real deployments.
Later in the video, the discussion shifts to pin-compatible module design, ODM work, early access to new SoCs, Linux support, and close collaboration with NXP, Rockchip, TI and Allwinner. That makes this less of a product showcase and more of a view into how embedded AI is being industrialized: standardised compute building blocks, faster bring-up, tighter software-hardware co-design, and a clearer route from demo to mass production. The video was filmed at Embedded World 2026 in Nuremberg, where Forlinx framed edge AI as a system integration problem as much as a silicon one.
Forlinx i.MX 95, Ara240 and RK3588 Edge AI for Vision and Local LLMs
Forlinx Embedded AI Platforms with i.MX 95, Ara240, RK3588 and
