HiSilicon K3V2 Quad-core 40nm ARM Cortex-A9

Posted by Charbax – February 27, 2012

Huawei's new high performance Diamond series phone uses the new HiSilicon K3V2 Quad-core 40nm ARM Cortex-A9, with 64bit latest/fastest DDR2-for-smartphone memory bandwidth, they claim it has the worlds fastest ARM performance. Here's an interview with the chief architect on the processor. I try to ask him about the performance, memory bandwidth, GPU, processor design. The K3V2 is made at the TSMC foundry. He has a team of about 500 processor engineers working for him in Shanghai to design this processor. He claims HiSilicon's cache coherent interconnect design makes it superior to designs such as Tegra3, HiSilicon does not need that "companion core" as they claim to have designed the Quad-core in "the correct way". HiSilicon has a GPU design partner which I have not heard them mention who it might be. In 6-12 months, HiSilicon is likely to release an ARM Cortex-A15 design on 28nm and also to upgrade their ARM Cortex-A9 designs to 28nm "when 28nm is ready", for now, he says that the 28nm process manufacturing has too much leakage.

  • Karel Gardas

    HiSilicon does not need that “companion core” as they claim to have designed the Quad-core in “the correct way” — actually I don’t believe in this claim. The thing is simple, this “companion” core is one of the best inovation of whole ARM industry. Don’t forget not only NVidia is using it, but ARM took it even little bit further with its BIG.little scheme using A15 cores together with A7 core. In fact this is the  killer feature where Intel cannot compete at all — well, if we consider that with intel’s latest fabs they can barely compete with their power hungry atoms to ARMs built on older processes…

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  • Anonymous

     Intel’s latest 32nm Medfield SoC FAB is, besides some performance tweaks, still based on the same ATOM architecture they’ve been using for years.  So should come at no surprise that ARM’s much more modern next gen offerings will outshine it.  However, they’re completely re-working the ATOM architecture next year with the 22nm Silvermont and finally making the ATOM up to date. 

    While Intel is apparently ahead in dealing with the power leakage issue as they continue to shrink the FAB that could start compensating them for their normal power efficiency disadvantage versus ARM.

    So it’s hard to say right now how this will play out.  We only know the next gen ARM offerings will likely become the best low cost solutions, barring legacy support, by the end of this year but next year is next year.

    Btw, I’ve seen some other sites incorrectly state this K3V2 quad core as being 64bit.  What it actually has is a 64bit memory bus and that’s one of the key reasons it can probably out perform the Tegra 3.

    I agree, the HiSilicon claim that the “companion core” is not needed is dubious and it remains to be seen how power efficient their solution is for a proper comparison. 

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  • Marc Guillot

    No, the best innovation of whole ARM industry is big.LITTLE Cortex-A15 / Cortex-A7 architecture.

    “Companion” core is like disable 3 cores and underclock the 4th.

  • Marc Guillot

    No, the best innovation of whole ARM industry is big.LITTLE Cortex-A15 / Cortex-A7 architecture.

    “Companion” core is like disable 3 cores and underclock the 4th.

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  • Toto

    Nice to read an article that say that’s HiSilcon Soc and not Huawei one (as copypasted most of technoblogs). These two companies works together since 2004 on ARM SoC.


    Thanks again Charbax.

  • NakTT

    What Karel Gardas said is right. I guess you are the one who get it wrongly.

  • titi

    you are right. big.Little is probably the most expensive way of doing things. You need two cluster + coherent interconnet (w/o directory) . This interconnect alone will probably consume more power that a Cortex A9 in LP process

  • Pug_ster

    There’s no such thing as 64 bit arm cpu’s.  It only exist on paper.  Nvidia, TI and Qualcomm all use 32 bit memory bandwidth in their SOC’s.  Though these SOC’s were able to compensate by using dual channel memory soc’s.  We will see if this phone is faster than the others as they claim.

  • Anonymous

     I already said this isn’t a 64bit chip, it only has a 64bit memory bus!

  • Hugo Becker

    I’m very curious about the “coherence” claim.  It would be quite interesting if it brings cache coherency out to the interconnect e.g. a PCIe connection, or if it is only cache coherent between cores by virtue of sharing the L2 cache.  My understanding is that using a licensed “netlist” core precludes the latter.  Coherence could be added by an architectural licensee that designed their own core, but that’s added expense and power draw that hasn’t (yet) been introduced.

    Does anyone know what the actual capabilities are?

  • Hugo Becker

     That should have been “precludes the former” or “results in the latter case”.

  • Marc Guillot

     Yeah !, because Tegra fifth core doesn’t need interconnect, ¿ right ?.

  • titi

    yes, of course. but two masters only instead of 3 masters. no coherency to support, no buffering to add to cope with snoop delays (CCI has no directory). And add one top of that two big L2 compared to 1. Which system is smaller , simpler, lower power ? 

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  • Jia Yi LI

    In fact HiSilicon is a subsidiary of Huawei..

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