Ezchip is preparing a 100 core ARM Cortex-A53 Processor, optimized for high-performance networking, 200-Gigabit throughput, hardware accelerators, Mesh cores interconnectivity for massive bandwidth, low latency and linear scalability. Barry Spinney, Network Architect at Ezchip talks about the 100-core ARM processor and shows a hardware-optimized ODP implementation running on the Tilera TILE-Gx 36-core processor with PCI-Express, Multiple memory controllers, hardware assist, hardware scheduler, crypto-engines, hardware traffic manager with many new hardware acceleration parts to be implemented in the 100-core ARM SoC. You can read more about it here: http://www.tilera.com/News/PressRelease/?ezchip=97