RISC-V CEO Andrea Gallo presents here not as a single chip vendor story, but as the governance layer behind an open instruction set architecture that lets semiconductor firms, IP providers, tool vendors and device makers build to the same ISA while keeping their own implementation details proprietary. The interview explains why that distinction matters: RISC-V is an open standard, not an open-source core, so the shared asset is the specification itself and the portability it enables across software stacks, supply chains and long product cycles. https://riscv.org/
A central theme is standardization. Andrea Gallo frames the 2025 milestone of RISC-V International becoming an ISO/IEC JTC 1 PAS submitter as more than a badge: it is a path toward formal international recognition for the ISA, which can matter in procurement, compliance, functional safety and regulated industrial design. That is especially relevant as RISC-V moves further from microcontrollers into application processors, automotive platforms, security architectures and compute infrastructure where interoperability and long-term governance carry real weight.
The conversation also gets into how technical consensus is built without turning the ISA into bloat. New extensions are expected to solve real multi-company problems, not one-off requests, and that discipline is what keeps the architecture coherent while still expanding into vectors, matrix processing and AI-friendly data handling. The software point is critical: vendors may differentiate in silicon, microarchitecture and performance, but developers still want one PyTorch, one TensorFlow backend, one toolchain target and a stable compliance model rather than fragmented ports.
Another useful insight is how RISC-V is organizing itself around both horizontal technologies and industry verticals. Alongside the core technical groups, the ecosystem is pulling in requirements from automotive, safety, data center, space, intelligent edge and robotics so that recommendations can map real workloads to the right ISA profiles, extensions and software expectations. That makes the story less about ideology and more about practical system design: where the standard should stop, where vendors should compete, and how to keep portability from compiler to firmware to OS and AI runtime.
What comes through most clearly is that RISC-V is no longer just a university-origin ISA associated with embedded experimentation. It is becoming a neutral coordination point for global compute development, backed by formal process, public technical review and a growing base of engineers, researchers and students who are treating the architecture as production infrastructure. Filmed at Embedded World 2026 in Nuremberg, this interview captures that transition well: from open ISA theory to the harder work of profiles, extensions, safety, matrix acceleration, ecosystem alignment and real deployment at scale.
