Veriest describes itself as a chip design partner for silicon vendors, spanning front-end architecture/RTL, back-end physical design, and low-level software that sits close to the silicon (BSP, drivers, bring-up, validation). The discussion frames “AI in semiconductors” as two parallel tracks: building AI accelerators into SoCs, and using AI to speed up the chip creation pipeline itself. https://www.veriests.com/
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On the “AI to build chips” side, the interview leans into agentic/autonomous systems that can take on repetitive engineering work: design verification, regression triage, log clustering, test generation, coverage closure, constraint hygiene, and debugging support across evolving codebases. The key caveat is data: useful models typically need large, domain-specific corpora (design histories, bugs, waveforms, assertions, sign-off reports), plus a human-in-the-loop loop to keep results trustworthy and aligned with project intent, not just fast work flow.
On the “building AI chips” side, it connects to the edge-AI reality that most embedded vendors now ship: SoCs with on-chip NPUs/NN accelerators tuned for latency, power, and thermal limits. That pushes practical questions into the foreground—operator placement, quantization, memory bandwidth, real-time scheduling, and which modality dominates (vision pipelines, audio inference, sensor fusion), because each drives a different compute/memory profile at the edge.
Later, recorded on the show floor at Embedded World North America 2025, the conversation also touches security as another dual-use mirror: applying AI to security (finding flaws, prioritizing fixes) while also securing AI (model integrity, update chains, and attack surfaces). In chip terms that can mean secure boot, root-of-trust, TEE isolation, side-channel awareness, and supply-chain discipline that protects both firmware and deployed models once devices are out there.
The overall takeaway is pragmatic: today’s AI won’t let you type “make me a 2 nm chip” and walk away, but it can meaningfully compress iteration cycles and reduce the grind in verification and bring-up as complexity keeps rising. If you’re watching the semiconductor stack converge with LLM tooling, NPUs, and safety/security requirements, this is a compact snapshot of where “agentic EDA” meets real product constraints today.
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