NEC explains why its long-running vector-computing lineage is now converging with a more open scalar ecosystem: building a successor to the company’s Vector Engine PCIe card that pairs NEC vector IP with a RISC-V control and system layer co-developed with Openchip. The point is pragmatic engineering rather than hype: vector math is a NEC strength, while RISC-V software stacks, tooling, and platform glue are easier to share across partners and regions. https://www.nec.com/en/global/solutions/hpc/sx/vector_engine.html
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To ground that story, the interview shows a working Vector Engine card and describes the underlying vector architecture that NEC has iterated for roughly four decades. The design is built around wide vector registers, high sustained throughput, and extreme memory bandwidth via on-card high-bandwidth memory, targeting workloads where data movement dominates. In the SX-Aurora TSUBASA line, Vector Engine specs reach up to 16 vector cores, up to 2.45 TB/s of memory bandwidth, and up to about 4.91 TFLOPS double-precision peak, depending on model and config, which sets the tone for the stack.
The Openchip board on the table is a mock-up, but the architectural direction is clear: a RISC-V scalar environment wrapped around a next-generation NEC vector processing unit so the card can look more like a standard Linux accelerator while keeping the vector datapath specialized. That enables cleaner compiler paths via LLVM/GCC, familiar MPI + OpenMP style programming, and room for tighter host integration through PCIe Gen5/Gen6 and CXL-era memory and coherency ideas. This segment was filmed at Supercomputing SC25 in St Louis, with the broader backdrop of Openchip–NEC work that has also been discussed publicly with HPC groups such as Barcelona Supercomputing Center, around RISC-V-based vector compute on a single card.
The same booth also hints at NEC’s dual role as both chip developer and system integrator, pointing to a Japanese “plasma” cluster concept that mixes mainstream CPUs and GPUs—think Intel Xeon-class parts alongside AMD Instinct MI300A-class accelerators—to chase strong performance per watt in the Green500 mindset. Put together, the thread is about heterogeneous compute as a design rule: CPUs for control, GPUs for throughput, and vectors for bandwidth-bound kernels, with RISC-V acting as the connective tissue for a longer-term, more portable software path.
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