Fujitsu walks through the roadmap from K computer (2011) to Fugaku (2020) and into FugakuNEXT, positioning it as a converged AI-HPC platform where classic simulation and modern AI pipelines share the same node architecture. The discussion centers on FUJITSU-MONAKA as the next CPU line, and MONAKA-X as the variant designed for tight GPU coupling, with a stated goal of large real-world application uplift rather than only peak FLOPS. https://www.fujitsu.com/global/about/research/technology/fujitsu-monaka/
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MONAKA is presented as an Arm-based many-core CPU family (Armv9-A), scaling beyond the A64FX era and targeting dense, energy-aware compute per rack. Public specs point to a 3D chiplet approach (compute + stacked SRAM/cache + I/O), a 2 nm compute die, and dual-socket configurations reaching 144 cores per socket, paired with modern memory and I/O like DDR5, PCIe 6.0 and CXL for balanced bandwidth per node.
MONAKA-X is about accelerating the AI-HPC “meeting point”: scalar control and irregular memory access on CPU, while pushing massively parallel matrix math to accelerators. Fujitsu highlights Arm SME (Scalable Matrix Extension) as an NPU-like matrix engine in its CPU story, then extends it with coherent, high-bandwidth CPU↔GPU integration via NVIDIA NVLink Fusion/NVLink, aimed at lowering latency and reducing data-copy overhead on the hot path.
At the system level, the slides split networking into scale-up communication inside a rack and scale-out communication between racks, acknowledging that the fabric is as critical as the compute silicon once you chase thousands of nodes. The conversation also touches on a more global posture for the next machine, and it was recorded on the Supercomputing 2025 show floor in St. Louis, where interoperability and ecosystem alignment are clearly part of the narrative here.
The “100× faster application performance over Fugaku” claim is framed as a software problem as much as a hardware one: compilers, profilers, math libraries, mixed-precision workflows, and performance-portable frameworks that can target CPU, GPU, and matrix extensions without rewriting everything. The timeline discussed is detailed design work through 2026–2027 and full operation around 2030, with an even more integrated “XX” CPU–NPU fusion hinted at but not yet disclosed in detail here.
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