NXP’s Mike Preser talks about the shift from cloud-only AI to edge inference, where ML runs directly on embedded silicon for lower latency, lower bandwidth, and tighter power budgets—especially in vision, audio, and sensor-fusion workloads that can’t always stream raw data upstream https://www.nxp.com/design/design-center/development-boards-and-designs/ARA-2-2M-MODULE
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A concrete example is pairing NXP platforms with Kinara’s Ara-2 neural accelerator, which targets up to 40 eTOPS for on-device inference. In practice that’s about pushing transformer and CNN workloads through quantized INT8/INT4 pipelines, keeping memory traffic and thermals under control while still enabling LLM, VLM, and multimodal perception close to the camera or gateway device
Rather than “edge vs cloud,” the pattern described is a split pipeline: train and evaluate in the cloud, then compile, calibrate, and deploy optimized models on-device, with selective telemetry back to the cloud for monitoring and continuous improvement. NXP leans heavily on software here—toolchains, SDKs, and ML runtimes, plus strong engagement with open source ecosystems like Zephyr RTOS to keep the developer stack portable
The broader context is also supply and geography: NXP is headquartered in Austin, while expanding Europe manufacturing alignment via the ESMC joint venture in Dresden with partners including TSMC, Bosch, and Infineon. Filmed on the Embedded World North America 2025 show floor, the takeaway is that edge AI is now less about “can it run” and more about repeatable deployment: performance-per-watt, software maturity, and a clean path from prototype to product
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