Micron uses this tour to argue that memory and storage, not just GPUs, now define AI and high-frequency-trading performance, explaining how its DRAM, CXL memory expansion and hyperscale NVMe SSDs are tuned to keep accelerators continuously fed with data. From 1-gamma DRAM wafers to next-generation PCIe Gen6 drives, the story is about latency, bandwidth and tiered capacity rather than only raw compute. https://www.micron.com/markets-industries/ai/ai-data-center
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On the memory side, Micron highlights its 1-gamma DRAM node, built with EUV lithography to deliver more than 30% higher bit density, lower power and higher speed than the previous 1-beta generation, and deployed across HBM3/HBM4 stacks, DDR5 RDIMMs and high-capacity MRDIMMs. The same technology underpins record-setting STAC-A2 and STAC-M4 benchmark systems for quantitative finance, where millisecond-level gains in risk calculations and tick-by-tick analytics can translate directly into trading edge.
The discussion then moves to CXL-based disaggregated memory: a chassis populated with Micron CXL memory cards behind an XCON switch, exposing around 15 TB of pooled capacity that can be shared across four servers. This creates a near-memory, main-memory and expansion-memory hierarchy, with access latency rising from roughly 100 ns on local DRAM to about 450 ns over CXL, still around 10× faster than going out to SSDs while offering far more capacity than on-board DIMM slots. That extra tier is presented as a way to keep data-hungry HPC and AI workloads in memory longer, reducing trips to storage while matching capacity to the economics of each application.
On the storage side, Micron shows its PCIe Gen6 9650 NVMe SSDs alongside a broad Gen5 data-center portfolio aimed at AI clusters and exascale storage. The Gen6 drives push up to roughly 28 GB/s sequential read bandwidth and 5.5 million random read IOPS in EDSFF E1.S and E3.S form factors, while the new 6600 ION QLC family targets capacity tiers with 122 TB today and 245 TB per drive on the roadmap, all built on G9 276-layer 3D NAND that scales from TLC to QLC depending on endurance and cost per bit.
Filmed at Supercomputing 2025 in St Louis, the conversation closes on system-level design: how ultra-dense SSDs can collapse racks of nearline HDDs into a few EDSFF enclosures, cutting power, cooling and floor space, and how enterprise endurance ratings of multiple drive writes per day over five years intersect with real-world bandwidth limits so that drives are rarely worn out. The Micron team also touches on GPU-direct storage paths that send data from NVMe through PCIe switches straight to accelerators, sustaining hundreds of millions of IOPS per server and keeping expensive compute silicon busy instead of idle.
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