Cypress PSoC 6 dual-core ARM Cortex-M4 and ARM Cortex-M0+

Posted by Charbax – March 17, 2017

The Cypress Semiconductor PSoC 6 is a dual-core microcontroller featuring all Cypress's peripherals and configurability of previous generations, to build low-power designs with a high degree of security, for IoT. Cypress PSoC 6 features ARM Cortex-M4 and ARM Cortex-M0+ cores, in an ultra-low-power 40-nm process technology, with integrated security features required for next-generation IoT. The architecture is intended to fill a gap in IoT offerings between power-hungry and higher-cost application processors and performance-challenged, single-core MCUs. The dual-core architecture lets designers optimize for power and performance simultaneously, alongside its software-defined peripherals. The two cores can achieve 22 µA/MHz and 15 µA/MHz of active power on the ARM Cortex-M4 and Cortex-M0+ cores, respectively. The dual-core architecture enables power-optimized system design where the auxiliary core can be used as an offload engine for power efficiency, allowing the main core to sleep.

The PSoC 6 MCU architecture provides a hardware-based Trusted Execution Environment (TEE) with secure boot capability and integrated secure data storage to protect firmware, applications and secure assets such as cryptographic keys. PSoC 6 implements a set of industry-standard symmetric and asymmetric cryptographic algorithms, including Elliptical-Curve Cryptography (ECC), Advanced Encryption Standard (AES), and Secure Hash Algorithms (SHA 1,2,3) in an integrated hardware coprocessor designed to offload compute-intensive tasks. The architecture supports multiple, simultaneous secure environments without the need for external memories or secure elements, and offers scalable secure memory for multiple, independent user-defined security policies.

Software-defined peripherals can be used to create custom analogue front-ends (AFEs) or digital interfaces for innovative system components such as electronic-ink displays. The architecture offers flexible wireless connectivity options, including fully integrated Bluetooth Low Energy (BLE) 5.0. The PSoC 6 MCU architecture features the latest generation of Cypress’ CapSense capacitive-sensing technology, enabling touch and gesture-based interfaces. The architecture is supported by Cypress’ PSoC Creator Integrated Design Environment (IDE) and the ARM ecosystem.

In this video, Cypress shows PSoC 6 using a wearable demo and the PSoC 6 pioneer kit. You can read more about PSoC 6 here: http://www.cypress.com/event/psoc-6-purpose-built-iots