Calypto high-level synthesis, RTL power optimization and functional verification

Posted by Charbax – November 3, 2013

Calypto Design Systems family of products enables ASIC, SOC and FPGA designers to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design. With Calypto’s Catapult High-Level Synthesis products, designers have the option of using SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, PPA optimized RTL. Calypto’s PowerPro product line enables users to analyze both static and dynamic power usage at RTL and either automatically or manually create a power optimized RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies the complete RTL without the need for time consuming simulation and complex testbenches. The end result is dramatic reduction in time to market with up to 60% reduction in power usage.

Contact Calypto:
Mathilde Karsenti
Marketing Programs Manager | Calypto Design Systems
1731 Technology Drive, Suite 340, San Jose, CA 95110
c: 503.970.7410

Stuart Clubb
US FAE Manager | Calypto Design Systems
8005 SW Boeckman Rd, Wilsonville, OR 97070
w: 503.685.1859 | f: 503.685.7832 | c: 503.701.6915 | www.calypto.com

Rob Eccles
Field Applications Engineer| Calypto Design Systems
1731 Technology Drive, Suite 340, San Jose, CA 95110
w: 408.477.8170