OPNFV Pharos Lab project deals with developing an OPNFV lab infrastructure that is geographically and technically diverse. The Pharos Lab is hosted in Kista, Sweden, it will greatly assist in developing a highly robust and stable OPNFV platform (see more: https://wiki.opnfv.org/pharos) OPNFV is a carrier-grade, integrated, open source platform to accelerate the introduction of new NFV products and services (see more: https://wiki.opnfv.org/start)
The following ARMv8 servers are used:
- Controller nodes: 3 * Applied Micro X-Gene 2 ARMv8-64 8 cores @ 2.4GHz, 32GB RAM, 1x128GB SSD, 2x1TB HDD, 1x10Gbps SFP+ NICs, 2x1Gbps NICs.
- Compute nodes: 2-3* Cavium Networks CN8890-CRB ThunderX ARMv8-64 48 cores @ 2.5GHz, 8x16GB RAM (128GB total), 1x500GB HDD, 1x40Gbps QSFP+ NIC, 2x10Gbps SFP+ NICs, 1x1Gpbs NIC (RJ45, IPMI interface).
ENEA’s demo in ARM booth was showing a simple NFV application running on our operational ARMv8 Pharos lab infrastructure. The application demonstrates a simple NFV service chain integrating a DPI (deep packet inspection) VNF engine provided by QOSMOS (see more: http://www.qosmos.com).
Cavium ThunderX 64bit 48-core ARM Server enabling the 5G mobile future, next gen cloud/datacenter and NFV
Cavium’s ThunderX 48-core ARMv8 64bit SoC is being implemented in dozens of ARM Server designs, by partners as Pegatron, Asus, Mitac, Gigabyte, Wiwynn, Acer and even for for super computing by E4 and Cray. Cavium and their software partners have optimized their ARM Server platform for variety of workloads, including NFV (Network Function Virtualization), Cloud RAN (Radio Access Network) for Virtualizing the access network, moving all the physical base stations to the cloud, which will save the industry a lot of money, hyperscale datacenter, web hosting like RunAbove (a subsidiary of OVH) at https://www.runabove.com/armcloud.xml, Ceph storage clusters. This can only be done using ARM and Cavium ThunderX SoC processors, providing a much better TCO (Total Cost of Ownership) and efficient alternative to Intel x86. Cavium and partners, as Linaro and the open source community also are showing progress in the OPNFV, OpenStack, ODP (Open Data Plane), DPDK, fd.io, etc. for the networking and telecom industry.
Functional demonstration of ODP-OpenvSwitch (ODP-OVS) running on ThunderX. ODP-OVS to process the upd pkt in loopback way on 10G port. Pkt generator pumps 10G traffic to ODP-OVS port. ODP-OVS receives pkts, validates pkt hash from ovs flow_table and then loopback to same port at 10G line rate.
Gigabyte shows their "fastest ARM Server in the world" solution, packing 384 cores into a standard 2U. Big cloud companies like Google, Facebook, Amazon could buy these to fill up their datacers with 11 thousand or 15 thousand of them. Gigabyte's ARM Server product manager talks about the performance, the features compared to the old fashioned Intel x86 servers, the power consumption is much lower. Gigabyte will launch the mass production in November, now providing samples for validation and testing by their big cloud company customers around the world. The 48-core ARM ThunderX Processor uses about 95W, while the comparative-performance Intel x86 based server processor consumes 145W, totally the saving is about 400W per 2U system, which means a potential saving of 8000W power per server rack. Gigabyte started using ThunderX in their R120-T30 single-socket server, moving to the dual socket design to be ready for taking over the massive cloud computing market.
Gigabyte is launching a whole range of ARM Powered Servers at Computex 2015: Gigabyte H279-T70 based on the Cavium ThunderX with 384 cores in a 2U system, Gigabyte D120-S3G featuring the Annapurna Labs Alpine AL5140 quad-core ARM Cortex-A15 and the Gigabyte R120-P30 is based on the Applied Micro X-Gene 1 Octa-core 64bit processor.
Cavium is showing the most powerful ARM Processor in the world, with a 48-core ARMv8 64bit processor, demonstrating the high-performance visualization running the Xen Hypervisor running on an internal evaluation board and the KVM Hypervisor running on a rack-mounted 1U platform.
Cavium demonstrates a high performance implementation of ODP-IPSec packet processing on a Cavium MIPS SoC on both Linux-Userspace and Bare Metal runtime environments. The demo is able to produce 40GB/s IPSec ESP processing.
Demonstrate the performance effective implementation of ODP-IPSec packet processing on Cavium SoC on Linux-Userspace and Bare Metal runtime environments.
IPSec ESP Processing (Authentication and Cipher)
40G Line rate
Linux User Mode environment support
Bare metal environment support
AES-CBC Cypher ( RFC 3602)
HMAC-SHA1-96 Authentication (RFC 2404)
Multiple SA support
Direct access to perf counters for Networking/ODP domain really helps to budgeting lower CPU cycles to Benchmark Data Plane. Demo shows POC about Accessing Perf counters with Perf syscall Vs Direct access of perf counters from Userspace. Implementation has been shown for ArmV7 ( Arndale ) Board and ArmV8 ( Juno ) Board. Yogesh Tillu, Linaro/Cavium Engineer has demoed 1st cut implementation of concept.
Cavium launches the world's fastest ARM Processor in their family of workload optimized ThunderX 64bit ARMv8 Server Processors (including ThunderX_CP for Cloud, ThunderX_ST for Storage, ThunderX_SC for Security and ThunderX_NT for Networking), for a range of applications in the cloud and data center. With 48 cores running at 2.5GHz each, ThunderX is the world’s highest performing low-power 64-bit ARMv8 SoC family of workload optimized processors with a range of SKUs and form factors for high performance volume compute, storage, secure compute and networking specific workloads. Analysts predict that the global data center infrastructure market, including servers, storage, networking, security and virtualization, will reach $128 billion in 2014. Cavium is hereby taking their share of that market by releasing their extremely high performance custom design ARM Server processor.
This product family is based on highly efficient full custom processor cores designed by Cavium in 28nm process technology under architectural license from ARM. It is fully compliant with ARMv8 architecture as well as ARM’s Server Base System Architecture (SBSA) standard while bringing to market dramatic enhancements that include:
-The first ARM based SoC that scales up to 48 cores with up to 2.5 GHz core frequency with 78K of I-Cache and 32K of D-Cache along with 16MB of L2 cache.
- The first ARM based SOC to be fully cache coherent across dual sockets using Cavium Coherent Processor Interconnect (CCPI™)
- Integrated I/O capacity with 100s of Gigabits of I/O bandwidth
- Four DDR3/4 72 bit memory controllers capable of supporting 2400 MHz memories with 1TB of memory in a dual socket configuration
- Hundreds of integrated hardware accelerators for security, storage, networking and virtualization applications.
- Standard based low latency Ethernet fabric interconnecting thousands of ThunderX™ nodes in 2D and 3D configurations and enabling fabric monitoring and SLA enforcements with awareness and policy enforcement for virtualized networks.
- Virtualization everywhere with Cavium virtSOC™ technology – Full system virtualization for low latency from virtual machine to I/O.
- Best in class performance per watt and performance per dollar for the target applications
Read more: press release
- Cavium announces 48-core ARMv8 server processor (techreport.com)
- Cavium packs 48 cores into ThunderX ARM chips (pcworld.com)
- Cavium Thunder X ups the ARM core count to 48 on a single chip (semiaccurate.com)
- Welcoming Cavium as latest Xen Project Advisory Board member (xen.org)
- Cavium ThunderX: 2.5 GHz, 48 Core ARMv8 SoC (phoronix.com)
- Cavium ThunderX ARM Chip Rumbles Into Hyperscale (enterprisetech.com)
- 48 Core ARM-64 processors from Cavium to challenge Xeons? (eetimes.com)
- 64-bit Cortex Platform To Take On x86 Servers In The Cloud (electronicdesign.com)
- Cavium sets sights on Intel with 48-core SoC (go.theregister.com)
- Cavium Announces Mainstream ARM Server Chips To Challenge Xeon (techweekeurope.co.uk)
Cavium talks about and shows their latest enterprise, data center, wired and wireless networking OCTEON and OCTEON Fusion SoCs based on ARMv8 64bit and MIPS, making customized optimized core designs for each in use for cloud servers and base stations among other. CAVIUM claims that their ARMv8 64bit enterprise/server design, due to be released later this year, provides more performance at lower power consumption than Intel´s x86.