LOl more than likely.

 i dont really like advocating http://www.phoronix-test-suite.com/ as the dev doesnt really add end user requests to the tests they want ,only listens to the commercial users,  but if someone techy with an existing rooted Tegra3 quad were to run the phoronix  tests then that would probably indicate Nvidia only use the cheaper slower ram , probably in the 6.4GB/s memory bandwidth or even less right now.

if Huawei can really claim theirs is 2x faster than a Tegra3, it wouldnt surprise me if they Simpy put faster 8.5 GB/s ram on their PCB to better match their SOC with other small tweaks.

I tried to ask the Nvidia people at CES and they didn’t want to tell me neither on or off camera how fast the memory bandwidth is for the Tegra3. Maybe it’s because they are still slower than OMAP4?

i have never bothered to look into the breakdown of each SOC vendor/model but it shouldn’t be to hard to find the info from the  various  Tear down Analysis reports of what ram manufacture and model are used on each if all else failed to get the ram models but OC you have to wait for a product to be make available retail that way usually.
 
 if you carried a portable magnifying glass and focused your cam closer and steadier when you film the PCB’s people could probably identify what’s in use from even that and then look up the real spec of the ram chips.

 it’s always far easier to ask the company tech if their around what the real spec of that chip and but  etc is , so thats why i mention it in case you forget

also see http://eda360insider.wordpress.com/2012/02/02/3d-thursday-boosting-the-bandwidth-of-wide-io-sdram-to-1-tbitsec-through-standards-evolution/ 

as that “Wide” I/O Interface with Extreme Bandwidth” is getting some large standards backing talk now for the future.

”
3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution
Posted on February 2, 2012 ”

“I want to focus on in this blog post is the issue of Wide I/O SDRAM. The JEDEC Wide I/O SDRAM spec (JESD229) calls for a 512-bit-wide data interface (split into four independent 128-bit channels) running at 266MHz with one transfer per clock cycle (single data rate signaling). 

This spec was created specifically for the low-power needs of mobile applications such as mobile phone handsets, where the total amount of energy available from a charged battery drives nearly all design decisions. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use”) ….”

Do we know the memory bandwidths of current ARM Cortex-A9 processors comparatively? Is the OMAP4430, OMAP4460, OMAP4470 faster than Tegra3, Tegra2, Exynos 4210, Exynos 4212, Exynos 4412, Apple A5? How about Qualcomm Krait?

remember  Charbax the No.1 key question that needs answers this year is what speed ram/bus is in on all this new A9/A15 SOC review kit at Mobile World Congress

are they still restricting total overall throughput by using cheaper limited single channel DDR, at approximately 3.2GB/s max, or far better dual channel LP DDR2 or best LP DDR3, running at what exact ram speeds etc, at a top speed up to 6.4GB/s memory bandwidth, or better 2-channel DDR3 @532 MHz with up to 8.5 GB/s  or better ?

 did anyone in 2012 finally fit and use the with Samsung “Wide” I/O Interface with Extreme Bandwidth
“The new 1Gb wide I/O mobile DRAM can transmit data at 12.8GB/s, which increases the bandwidth of mobile DDR DRAM (1.6GB/s) eightfold, while reducing power consumption by approximately 87% 
http://www.xbitlabs.com/news/memory/display/20110222201121_Samsung_Develops_Mobile_Memory_with_Wide_I_O_Interface_Extreme_Bandwidth.html

in other words how does their kit with their chosen ram speed match or better the generic PandaBoard ES running ARM On Ubuntu 12.04  runing the generic Ubuntu 12.04 development snapshot with the Linux 3.2 kernel and the http://www.phoronix-test-suite.com/ tests as the base line test today?
see http://www.phoronix.com/scan.php?page=article&item=ubuntu_1204_armfeb&num=1