Nordic Semiconductor is showing various demos showcasing their nRF52 series microcontrollers, showcasing the nRF52840 specifically, which supports all the new features introduced in Bluetooth 5.0, while also adding 802.15.4 and Thread support to the Nordic platform.
Nuvoton M2351 is a secure microcontroller platform powered by ARM Cortex-M23 core with ARMv8-M architecture, TrustZone technology, security technologies, peripherals and tools. The ultra-low-power 32-bit microcontroller works in low voltage range from 1.62V to 3.6V and can operate at up to 48 MHz frequency, with up to 512 Kbytes embedded Flash memory in dual bank mode supporting OTA firmware update and up to 96 Kbytes embedded SRAM. It is suitable for applications such as IoT secure connections, fingerprint authentication, EMV card reader, security alarm system, smart home appliance, wireless sensor node device (WSND), auto meter reading (AMR) and portable wireless data collector.
The M2351 series is equipped with 32 Kbytes Secure Boot ROM as root of trust, multiple firmware programming tools by In-System Programming (ISP), In-Circuit Programming (ICP) and In-Application Programming (IAP). In addition to TrustZone software protection mechanism, it also supports eXecution Only Memory (XOM), LDROM (user program loader) and multiple cryptographic hardware accelerators which are used to protect the core software and data assets on a microcontroller system. The M2351 series also integrates a 8 COM x 40 SEG controller with internal charge pump for segment LCD panel and provides high performance connectivity peripheral interfaces such as UART, SPI, I²C, GPIOs, USB and ISO 7816-3 for smart card reader.
As to Power efficiency, the M2351 series supports Brown-out detector, Power-down mode with RTC turn on, RAM retention less than 2.0 uA, deep power-down mode with RAM retention less than 1 uA and fast wake-up via multiple peripheral interfaces.
ARM Cortex-M23 TrustZone Technology
8 Memory Protection Units (MPU)
8 Security Attribution Units (SAU)
Implementation Defined Attribution Unit (IDAU)
2 KB OTP ROM with additional 1KB lock bits
Hardware Crypto Accelerators
CRC calculation unit
Up to 6 tamper detection pins
96-bit Unique ID (UID), 128-bit Unique Customer ID (UCID)
Matt Locke, Director of the Linaro IoT and Embedded Group (LITE) and Maureen Helm of NXP, one of the maintainers of the Zephyr Project which is a Linux Foundation hosted open source collaboration project, uniting leaders from across the industry to build a best-in-breed small, scalable, real-time operating system (RTOS) optimized for resource constrained devices, across multiple architectures. The Zephyr Project’s goal is to establish a neutral project where silicon vendors, OEMs, ODMs, ISVs, and OSVs can contribute technology to reduce the cost and accelerate time to market for developing the billions of devices that will make up the majority of the Internet of Things of the future.
The Zephyr Project is perfect for building simple connected sensors, LED wearables, up to modems and small IoT wireless gateways. Because the Zephyr OS is modular and supports multiple architectures, developers are able to easily tailor an optimal solution to meet their needs. As a true open source project, the community can evolve the project to support new hardware, developer tools, sensor and device drivers. Enhancements in security, device management capabilities, connectivity stacks and file systems can be easily implemented.
ST shows their best-in-class ultra-low-power STM32L4 microcontroller which delivers 100 DMIPS based on its ARM Cortex-M4 core with FPU and ST ART Accelerator at 80 MHz offering dynamic voltage scaling to balance power consumption with processing demand, low-power peripherals (LP UART, LP timers) available in Stop mode, safety and security features, smart and numerous peripherals, advanced and low-power analog peripherals such as op amps, comparators, LCD, 12-bit DACs and 16-bit ADCs (hardware oversampling). STM32L4 is available in these skews: STM32L4x1 (Access line), STM32L4x2 (USB Device), STM32L4x3 (USB Device, LCD), STM32L4x5 (USB OTG) and STM32L4x6 (USB OTG, LCD).
ST also shows their new STM32H7 platform, taking advantage of an L1 cache, STM32H7 can deliver the maximum theoretical performance of the ARM Cortex-M7 core, regardless if code is executed from embedded Flash or external memory: 2010 CoreMark /856 DMIPS at 400 MHz fCPU. STM32H7 supports AXI and multi-AHB bus matrixes for interconnecting core, peripherals and memories, 16 Kbytes +16 Kbytes of I-cache and D-cache, Up to 2 Mbytes of embedded dual-bank Flash memory, with ECC and Read-While-Write capability, high-speed master direct memory access (MDMA) controller, two dual-port DMAs with FIFO and request router capabilities for optimal peripheral management, and one additional DMA, Chrom-ART acceleration for efficient 2D image copy and double-precision FPU are also part of the acceleration features available in the device, peripheral speed independent from CPU speed (dual-clock support) allowing system clock changes without any impact on peripheral operations, even more peripherals, such as four serial audio interfaces (SAI) with SPDIF output support, three full-duplex I²S interfaces, a SPDIF input interface supporting four inputs, two USB OTG with dedicated power supply and Dual-mode Quad-SPI interface, two FD-CAN controllers, a high-resolution timer, a TFT-LCD controller, a JPEG codec, two SDIO interfaces and many other analog peripherals including three fast 14-bit ADCs, two comparators and two operational amplifiers. STM32H7 has 1 Mbyte of SRAM with a scattered architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes, Security Authenticate and protect software IP while performing initial programming in production or firmware upgrades in the field.
This ST booth tour video at Embedded World 2017 in Nuremberg also features several demos from the STM32 Fan Zone area at Embedded World 2017 featuring demos including a Gameboy emulator and a color LED light display system from students from the Thomas More college, Seavus smart Shopping cart, Bixi gesture controls in the car, Xped IoT systems and ST is giving away more than 5000 development boards at the Embedded World.
BeagleBone Blue is as a new Robotics and IoT development board based around the Octavo Systems OSD3358 System-In-Package featuring a Texas Instruments AM3358 1GHz ARM Cortex-A8, 512MB of DDR3 and power management enabling easy and affordable customization and re-design of the PCB using Autodesk EAGLE. BeagleBone Blue has 2 cell (2S) onboard LiPo battery management with charger and battery level LEDs, 8 real-time software controlled PWM/PPM outputs for 6V servo motors or electronic-speed-controllers (ESCs), 4 PWM-enabled DC motor drivers, 4 quadrature encoder inputs, on-board sensors including a 9-axis IMU and barometer, a wide array of GPIO and serial protocol connectors including CAN, 4 ADC inputs, a PC USB interface, a USB 2.0 host port, a reset button, a power button, two user configurable buttons and eleven user configurable LED indicators. BeagleBone Blue can run Debian, ROS, Ardupilot, Graphical programming, Cloud9 IDE on Node.js and more to come. You can order the BeagleBone Blue for $79 at https://www.arrow.com/en/products/bbblue/beagleboardorg
Nvidia Tegra X2 features two Nvidia custom Denver 2 cores, four ARM Cortex-A57 cores with Nvidia's Pascal GPU (made of 256 CUDA cores) made on TSMC's 16nm FinFET+. Nvidia Tegra X2 (codenamed "Parker") delivers up to 1.5 teraflops of performance, about 50% more performance than Nvidia Tegra X1. Enabling Artificial Intelligence (AI), for building advanced robots, drones, smart cameras, portable medical devices, enabling the processing of complex deep neural networks on the edge of the IoT world. While X1 could do 4K at 30fps encode, 4K 10bit 60p decode, X2 can encode 4K H265 at 60p and decode 4K 12bit 60p. Memory bandwidth has more than doubled from 25.6GB/s to 58.3GB/s, you can buy the Nvidia Jetson TX2 Developer Kit for $599 at https://store.nvidia.com/store?Action=DisplayPage&Locale=en_US&SiteID=nvidia&id=QuickBuyCartPage
The Cypress Semiconductor PSoC 6 is a dual-core microcontroller featuring all Cypress's peripherals and configurability of previous generations, to build low-power designs with a high degree of security, for IoT. Cypress PSoC 6 features ARM Cortex-M4 and ARM Cortex-M0+ cores, in an ultra-low-power 40-nm process technology, with integrated security features required for next-generation IoT. The architecture is intended to fill a gap in IoT offerings between power-hungry and higher-cost application processors and performance-challenged, single-core MCUs. The dual-core architecture lets designers optimize for power and performance simultaneously, alongside its software-defined peripherals. The two cores can achieve 22 µA/MHz and 15 µA/MHz of active power on the ARM Cortex-M4 and Cortex-M0+ cores, respectively. The dual-core architecture enables power-optimized system design where the auxiliary core can be used as an offload engine for power efficiency, allowing the main core to sleep.
The PSoC 6 MCU architecture provides a hardware-based Trusted Execution Environment (TEE) with secure boot capability and integrated secure data storage to protect firmware, applications and secure assets such as cryptographic keys. PSoC 6 implements a set of industry-standard symmetric and asymmetric cryptographic algorithms, including Elliptical-Curve Cryptography (ECC), Advanced Encryption Standard (AES), and Secure Hash Algorithms (SHA 1,2,3) in an integrated hardware coprocessor designed to offload compute-intensive tasks. The architecture supports multiple, simultaneous secure environments without the need for external memories or secure elements, and offers scalable secure memory for multiple, independent user-defined security policies.
Software-defined peripherals can be used to create custom analogue front-ends (AFEs) or digital interfaces for innovative system components such as electronic-ink displays. The architecture offers flexible wireless connectivity options, including fully integrated Bluetooth Low Energy (BLE) 5.0. The PSoC 6 MCU architecture features the latest generation of Cypress’ CapSense capacitive-sensing technology, enabling touch and gesture-based interfaces. The architecture is supported by Cypress’ PSoC Creator Integrated Design Environment (IDE) and the ARM ecosystem.
In this video, Cypress shows PSoC 6 using a wearable demo and the PSoC 6 pioneer kit. You can read more about PSoC 6 here: http://www.cypress.com/event/psoc-6-purpose-built-iots
ARM announces that 100 Billion ARM Processors have shipped. And in this video, ARM talks about their acquisition of Swedish Mistbase and British NextG-Com to enable ARM's new Cordio-N NB-IoT narrowband IoT communications standard.
Marc Moreno Berengue of ARM at Linaro Connect 2017 in Budapest shows TrustZone for ARM Cortex-M33 implementing a secure gateway between the Secure and Non-secure areas on the ARM Cortex-M33 SoC, with the ARM CoreLink SSE-200 subsystem, TrustZone, ARM CoreLink SIE-200, instruction cashes, power infrastructure components, Secure Debug with ARM CoreSight SoC, the optional ARM TrustZone CryptoCell and the optional ARM Cordio Radio. All these enabling security for IoT. This demonstration is running on the ARM Cortex-M Prototyping System (MPS2/MPS2+) which is a Versatile Express development board featuring a large FPGA for prototyping Cortex-M based designs and a range of different options for debug.