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Bero shows AOSP TV 8.1, Gemini PDA, Android with newer kernels at Linaro LMG/LHG hacking room

Posted by Charbax – March 24, 2018

Bero (Bernhard Rosenkränzer) and his colleagues from the Linaro Mobile Group (Android) and the Linaro Home Group (TV Boxes) are working in the hacking room at Linaro Connect to prepare some demos for Demo Friday including AOSP TV on 8.1 (while most Android TV runs on 7.1), updating the Linux kernel on Android phones to some newer kernel version, and Bero also gives his opinions on the multi-Linux booting Gemini PDA amazing keyboard phone which he has purchased (see my video on Gemini PDA Linux support here)

Tomas Evensen, Xilinx CTO of Embedded Software at Linaro Connect

Posted by Charbax – March 24, 2018

Tomas Evensen talks about FPGA, the Xilinx Ultra96 development board to be available at $249 (also see my video with Xilinx about Ultra96 here) and the announcement by Xilinx of their upcoming 7nm FPGA with ARM cores SoCs to come in 2019 with up to 50 Billion transistors on the SoC.

$99 Rock960 Enterprise Edition “Ficus”, Rock960 Pro with RK3399Pro with NPU for AI

Posted by Charbax – March 22, 2018

Tom Cubie of Vamrs introduces two new Rockchip RK3399Pro based development boards with at Linaro Connect Hong Kong 2018, a new ecosystem of development boards for Artificial intelligence development, where the new Rockchip RK3399Pro includes an NPU (2.4 TOPS capable NPU) teamed up with Open AI Lab (who I interviewed here) to support the AI framework.

Rockchip has now officially joined 96Boards as Steering Committee member, which means ROCK960 and other futures 96rocks boards based on Rockchip processors now have official identity in the 96boards/linaro community.

ROCK960 Enterprise Edition board runs Rockchip RK3399Pro hexa core dual ARM Cortex-A72, quad ARM Cortex-A53, Mali-T860MP4 GPU with 2.4 TOPS capable NPU, up to 4GB RAM, Dual SATA 3.0 port with RAID 0/1 support, HDMI 2.0/eDP up to 4K @ 60 Hz, Dual MIPI CSI camera interfaces, Gigabit Ethernet, 802.11ac WiFi, 3x USB 3.0, 5x USB 2.0, PCIe 2.1 x16 slot and more.

Rock960 consumer edition which I previously also filmed here is about to be manufactured now to be available next month.

Xilinx Ultra96, UltraScale+ FPGA 96Boards development board

Posted by Charbax – March 22, 2018

Ultra96 is an Arm-based, Xilinx Zynq UltraScale+ MPSoC development board based on the Linaro 96Boards specification. The 96Boards’ specifications are open and define a standard board layout for development platforms that can be used by software application, hardware device, kernel, and other system software developers. Ultra96 represents a unique position in the 96Boards community with a wide range of potential peripherals and acceleration engines in the programmable logic that is not available from other offerings.

Ultra96 boots from the provided Delkin 16 GB MicroSD card, pre-loaded with PetaLinux. Engineers have options of connecting to Ultra96 through a Webserver using integrated wireless access point capability or to use the provided PetaLinux desktop environment which can be viewed on the integrated Mini DisplayPort video output. Multiple application examples and on-board development options are provided as examples.

Ultra96 provides four user-controllable LEDs. Engineers may also interact with the board through the 96Boards-compatible low-speed and high-speed expansion connectors by adding peripheral accessories such as those included in Seeed Studio’s Grove Starter Kit for 96Boards.

Micron LPDDR4 memory provides 2 GB of RAM in a 512M x 32 configuration. Wireless options include 802.11b/g/n Wi-Fi and Bluetooth 4.2 (provides both Bluetooth Classic and Low Energy (BLE)). UARTs are accessible on a header as well as through the expansion connector. JTAG is available through a header (external USB-JTAG required). I2C is available through the expansion connector.

Ultra96 provides one upstream (device) and two downstream (host) USB 3.0 connections. A USB 2.0 downstream (host) interface is provided on the high speed expansion bus. Two Microchip USB3320 USB 2.0 ULPI Transceivers and one Microchip USB5744 4-Port SS/HS USB Controller Hub are specified.

The integrated power supply generates all on-board voltages from an external 12V supply (available as an accessory).

Cadence HiFi DSP SDK for Android

Posted by Charbax – March 22, 2018

Raj Pawate, Niranjan Yadla and Sachin Ghanekar presented a low cost SDK for Cadence HiFi 3 DSP. This Hikey960 development board enables software developers to leverage the power of the HiFi 3 DSP and introduce new algorithms for audio and speech processing. With HiFi 3 DSP running at 533 MHz and access to a large shared system memory of 13MB, software developers are no longer constrained to showcase their advanced algorithms. In addition, the HiFi 3 DSP works closely with an App processor hosting Android allowing software developers to integrate DSP functionality within the context of Android Applications.

Daniel Thompson Keynote: using the Arm Developer Box as main development box for 4 months

Posted by Charbax – March 22, 2018

Daniel Thompson talks about his use of the Socionext 24-core ARM Cortex-A53 based Arm Developer Box over the last 4 months, to do all the things that he needs to do for development.

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Shane Coughlan Keynote, OpenChain Project Director at The Linux Foundation at Linaro Connect 2018

Posted by Charbax – March 22, 2018

HKG18-400K2 – Keynote: Shane Coughlan with guest speaker Lucien Cheng-hsia Lin- Complex Made Simple: The State of Governance in Open Source

Clear governance, a shared understanding of process and rules, is key to the success of open source adoption at scale. Our global community represents many perspectives, many cultures and many jurisdictions. To address these we have seen the emergence of overarching principles, practical guides and effective tools that support the necessary balance of flexibility and shared trust. This talk will focus in the key open source solutions that address real world challenges. It highlights a stack of solutions that includes OpenChain, SPDX, Reuse.Software, FOSSology, ScanCode, sw360 and QuarterMaster and explain how they work together from meta level (e.g OpenChain standard) to practical process implementation (e.g QuarterMaster CI/CD).

For the last 10 minutes of Shane’s keynote, Lucien Cheng-hsia Lin discusses License Compliance in Asia.

The OpenChain Project identifies key recommended processes for effective open source management. The project builds trust in open source by making open source license compliance simpler and more consistent.

The OpenChain Specification defines a core set of requirements every quality compliance program must satisfy. The OpenChain Curriculum provides the educational foundation for open source processes and solutions, whilst meeting a key requirement of the OpenChain Specification. OpenChain Conformance allows organizations to display their adherence to these requirements.

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HiSilicon Open Source Keynote: Kenneth Lee, Chief Software Architect at Linaro Connect

Posted by Charbax – March 22, 2018

This talk explains why a commercial organization should join the open source development from the software architecture and commercial competition perspective. And it will also tell how a bad open source strategy will fail the original target.

Kenneth (Liguozhu) Lee / Hisilicon
Kenneth Lee is the chief software architect of Hisilicon. He has more than 14 years experience on OS and OS middleware design and development. He has worked on OS area for most of HUAWEI products which include wideband/Narrowband switches, routers, mobile phones, wireless stations, core network servers, etc. He is also the architect of HUAWEI’s first Linux distribution for lots of embedded telecom devices.

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Xilinx FPGA Keynote at Linaro Connect Hong Kong 2018

Posted by Charbax – March 21, 2018

HKG18-300K2 – Keynote: Tomas Evensen – All Programmable SoCs? – Platforms to enable the future of Embedded Machine Learning

As Moore’s law is slowing down, heterogeneous architectures are needed to keep up with the increasing compute requirements emerging from industry trends such as the use machine learning across a diverse range of markets and applications. These compute requirements require custom system architectures to suit the rapidly evolving demands of emerging algorithms, standards and trends.
Field Programmable hardware offers a unique capability to provide flexibility alongside advanced processor architectures to address this ever increasing multitude of applications. Development flows, programmability and flexibility are crucial to the enablement of these advancing algorithms and to enable the next generation of implementations in a world of advancing Artificial intelligence.
In this session we will introduce you to an all Programmable paradigm and low cost development platform to enable an ecosystem of flexibility and unparalleled programmability.
The future is now……

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Microsoft Azure on Arm Servers Keynote at Linaro Connect Hong Kong 2018

Posted by Charbax – March 21, 2018

HKG18-300K1 – Keynote: Leendert van Doorn “Microsoft Azure: Operating at Hyper-Scale”

At scale everything changes. It is one thing to operate a datacenter of 10K nodes, it’s an entirely different thing to operate millions of nodes across 100’s of datacenters around the world. What works well for enterprises doesn’t necessarily work at scale.

Microsoft is currently deploying their 6th generation platform designs and at each generation their insights improve and in some cases entirely change leading to many specific requirements to silicon vendors, ODMs and system integrators. Over the years Microsoft effectively had to become its own OEM where they manage the entire system design from sheet metal, motherboards, firmware, hypervisors, operating systems, management stacks and corresponding higher-level services. They do this so they can control cost, quality, reduce complexity and drive their innovations.

In this talk he takes people through some of the lessons learned when Microsoft Azure’s scale increased over the years. He presents some of the rationale behind their ARM64 server plans and specifically the rational behind some of their ARM64 silicon requirements.

Leendert van Doorn is a distinguished engineer in Microsoft’s Azure organization where he is running a set of hyper-scale incubation projects. Before joining Microsoft he was a Corporate VP/Fellow at AMD driving various software and hardware initiatives. Leendert holds a Ph.D. from the Vrije Universiteit in Amsterdam, The Netherlands.

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